74HC4059D,118 NXP Semiconductors, 74HC4059D,118 Datasheet - Page 7

• Manufacturer Part Number: 74HC4059D,118
• Description: IC PROG DIV-BY-N COUNTER 24SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr
• Type: Decader

Specifications of 74HC4059D,118

• Package / Case: 24-SOIC (7.5mm Width)
• Logic Type: Divide-by-N
• Direction: Down
• Number Of Elements: 1
• Number Of Bits Per Element: 16
• Reset: Asynchronous
• Timing: Synchronous
• Count Rate: 43MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counter Type: Decade Counters
• Logic Family: 74HC
• Counting Method: Synchronous
• Counting Sequence: Down
• Operating Supply Voltage: 2 V to 6 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 5
• Logical Function: Counter/Divider
• Operating Supply Voltage (typ): 5V
• Output Type: Standard
• Package Type: SOIC W
• Propagation Delay Time: 300ns
• Operating Temp Range: -40C to 125C
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74HC4059D-T; 74HC4059D-T; 933757410118

Philips Semiconductors
FUNCTION TABLE
Note
1. It is recommended that the device is in the master preset mode (K
Table 1
Table 2
Table 3
1998 Jul 08
LATCH
ENABLE
INPUT
LE
H
H
H
H
H
L
L
L
L
L
H
L
X
J
L
J
L
J
H
1
1
1
Programmable divide-by-n counter
device prior to start-up. An example of a suitable external circuit is shown in Fig.14.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
J
L
J
H
J
L
2
2
2
4
6
K
H
L
H
L
H
H
L
H
L
H
L
L
X
SELECT
a
INPUTS
MODE
9
K
H
H
L
L
H
H
H
L
L
H
H
H
L
J
H
J
H
J
L
b
3
3
3
K
H
H
H
H
L
H
H
H
H
L
L
L
L
c
MODE
2
4
5
8
10
2
4
5
8
10
10
J
H
J
H
J
H
4
4
4
1
1
FIRST COUNTING
preset inhibited
master preset
DECADE 1
MAX
PRESET
1
3
4
7
9
1
3
4
7
9
9
J
H
J
H
J
H
SECTION
STATE
5
5
5
J
L
J
H
J
H
6
6
6
JAM
INPUTS
USED
J
J
J
J
J
J
J
J
J
J
J
1
1
1
1
1
1
1
1
1
1
1
J
J
J
J
J
J
J
J
J
2
2
2
2
2
2
2
2
2
5
7
7
J
J
J
J
J
J
J
J
H
J
H
J
H
3
3
3
3
3
3
3
7
7
7
J
J
J
4
4
4
8
4
2
2
1
8
4
2
2
1
1
DIVIDED
J
L
J
L
J
L
BY
8
8
8
LAST COUNTING
preset inhibited
master preset
7
DECADE 5
J
H
J
L
J
L
SECTION
MAX.
PRESET
7
3
1
1
0
7
3
1
1
0
0
9
9
9
STATE
J
L
J
L
J
L
10
10
10
b
JAM
INPUTS
USED
J
J
J
J
J
J
J
J
= K
2
3
4
4
2
3
4
4
J
J
J
J
9
4
4
3
4
3
4
c
J
J
J
L
J
H
J
H
4
4
11
11
11
= logic 0) in order to correctly initialize the
BCD
MAX.
fixed
10 000
15 999 17 331
15 999 18 663
15 999 21 327
15 999 17 331
15 999 18 663
15 999 21 327
9 999 13 329
9 999 16 659
9 999 13 329
9 999 16 659
9 999 16 659
J
H
J
L
J
L
12
12
12
COUNTER
RANGE
BINARY
MAX.
J
L
J
H
J
L
13
13
13
74HC/HCT4059
J
H
J
L
J
L
Product specification
14
14
14
timer mode
divide-by-n mode
divide-by-10 000
mode
master preset
mode
OPERATION
6
5
8
J
H
J
H
J
L
15
15
15
J
L
J
L
J
H
16
16
16