74HC4059D,118 NXP Semiconductors, 74HC4059D,118 Datasheet - Page 13

• Manufacturer Part Number: 74HC4059D,118
• Description: IC PROG DIV-BY-N COUNTER 24SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCr
• Type: Decader

Specifications of 74HC4059D,118

• Package / Case: 24-SOIC (7.5mm Width)
• Logic Type: Divide-by-N
• Direction: Down
• Number Of Elements: 1
• Number Of Bits Per Element: 16
• Reset: Asynchronous
• Timing: Synchronous
• Count Rate: 43MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Counter Type: Decade Counters
• Logic Family: 74HC
• Counting Method: Synchronous
• Counting Sequence: Down
• Operating Supply Voltage: 2 V to 6 V
• Operating Temperature Range: - 40 C to + 125 C
• Mounting Style: SMD/SMT
• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 5
• Logical Function: Counter/Divider
• Operating Supply Voltage (typ): 5V
• Output Type: Standard
• Package Type: SOIC W
• Propagation Delay Time: 300ns
• Operating Temp Range: -40C to 125C
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74HC4059D-T; 74HC4059D-T; 933757410118

Philips Semiconductors
The arrangement shown in Fig.12 is easy to follow; once
during every cycle the programmed digits are jammed in
(15 616 in this example) and then a round number of
11 000 is jammed in, nine times in succession, by forcing
the JAM inputs via AND/OR gates.
Numbers larger than the extended counter range can also
be produced by cascading the PC74HC/HCT4059 with
some other counting devices. Figure 13 shows such an
arrangement where only one fixed divide-by number is
desired. The dual flip-flop wired to produce a divide-by-3
count can be replaced by other counters such as the “190”,
“191”, “192”, “193”, “4017”, “4510” and “4516”.
1998 Jul 08
Programmable divide-by-n counter
13
In Fig.13 the divide-by-n sub-system is preset once to a
number which represents the least significant digits of the
divide-by number (15 690 in the example shown in Fig.13).
The sub-system is then preset twice to a round number
(8 000 in the example shown in Fig.13) and multiplied by
the number of the divide-by mode (2 in the example shown
in Fig.13).
To verify:
15 690 2 8 000 2 = 47 690.
It is important that the second counting device has an
output that is HIGH or LOW during only one of its counting
states.
74HC/HCT4059
Product specification