MACH4 Lattice, MACH4 Datasheet - Page 9

• Manufacturer Part Number: MACH4
• Description: High Performance E 2 CMOS In-System Programmable Logic
• Manufacturer: Lattice

Note that the configuration of the logic allocator has absolutely no impact on the speed of the
signal. All configurations have the same delay. This means that designers do not have to decide
between optimizing resources or speed; both can be optimized.
If not used in the cluster, the extra product term can act in conjunction with the basic cluster to
provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flip-
flop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to
another macrocell, the extra product term is still available for logic. In this case, the first XOR
input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without
giving up the use of the macrocell.
Product term clusters do not “wrap” around a PAL block. This means that the macrocells at the
ends of the block have fewer product terms available.
a. Basic cluster with XOR
a. Basic cluster with XOR
single-product-term, active high
d. Basic cluster routed away;
single-product-term, active high
d. Basic cluster routed away;
Figure 4. Logic Allocator Configurations: Asynchronous Mode
Figure 3. Logic Allocator Configurations: Synchronous Mode
0
0
b. Extended cluster, active high
b. Extended cluster, active high
MACH 4 Family
e. Extended cluster routed away
e. Extended cluster routed away
c. Extended cluster, active low
c. Extended cluster, active low
17466G-007
17466G-008
9