MACH4 Lattice, MACH4 Datasheet - Page 12

• Manufacturer Part Number: MACH4
• Description: High Performance E 2 CMOS In-System Programmable Logic
• Manufacturer: Lattice

Note:
1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator
allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product
terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the
extra product term must be used on the XOR gate input for flip-flop emulation. In any register
type, the polarity of the inputs can be programmed.
The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode,
with the additional choice of either polarity of an individual product term clock in the
asynchronous mode.
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous
reset and preset are provided, each driven by a product term common to the entire PAL block.
12
D-type Register
T-type Register
D-type Latch
Product Terms
Initialization
PAL-Block
Configuration
a. Power-up reset
Power-Up
Reset
Figure 7. Synchronous Mode Initialization Configurations
D/T/L
AP
Table 8. Register/Latch Operation
Input(s)
AR
Q
D=X
D=0
D=1
D=X
D=0
D=1
T=X
T=0
T=1
17466G-012
MACH 4 Family
Product Terms
Initialization
PAL-Block
0,1,
0, 1,
CLK/LE
1(0)
0(1)
0(1)
1
Power-Up
b. Power-up preset
Preset
D/L
AP
Q+
Q
Q
Q
Q
Q
0
1
0
1
17466G-013
AR
Q