MACH210A-12VC Lattice, MACH210A-12VC Datasheet - Page 27

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MACH210A-12VC

Manufacturer Part Number
MACH210A-12VC
Description
High-Density EE CMOS Programmable Logic
Manufacturer
Lattice
Datasheet

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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
(continued)
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
2. See Switching Test Circuit, for test conditions.
Parameter
Symbol
where capacitance may be affected.
t
t
t
t
t
t
WIGL
PDLL
t
t
ARW
ARR
t
APW
t
APR
AR
ER
AP
EA
Parameter Description
Input Latch Gate Width LOW
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 1)
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 1)
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable
Input, I/O, or Feedback to Output Disable
MACH210AQ-12 (Com’l)
Min
19
19
19
19
6
-12
Max
18
24
24
12
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27

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