MACH210A-7VC Lattice Semiconductor Corp., MACH210A-7VC Datasheet
MACH210A-7VC
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MACH210A-7VC Summary of contents
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... FINAL MACH210A-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 44 Pins 64 Macrocells 7 Commercial Industrial PD 133 MHz f CNT 38 Inputs; 210A Inputs have built-in pull-up resistors GENERAL DESCRIPTION The MACH210 is a member of the high-performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed ...
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BLOCK DIAGRAM I/O –I I/O Cells 8 8 Macrocells Macrocells AND Logic Array and Logic Allocator AND Logic Array and Logic Allocator OE Macrocells Macrocells 8 8 I/O ...
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CONNECTION DIAGRAM Top View I/O 5 I GND CLK I/O 8 I/O 9 I/O 10 I/O 11 Note: Pin-compatible with MACH110, MACH111, MACH211, and MACH215. PLCC ...
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CONNECTION DIAGRAM Top View I/O5 I/O6 I/ GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 Note: Pin-compatible with MACH111 and MACH211. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply ...
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... MACH210A-7 JC, MACH210A-10 VC MACH210A-12 MACH210-12 MACH210-15 MACH210-20 JC MACH210AQ-12 MACH210AQ-15 MACH210AQ-20 MACH 210A -7 J The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult your local sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations. ...
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... Macrocells, 44 Pins, Input Pull-Up Resistors SPEED - - Valid Combinations MACH210A-12 MACH210A-14 JI MACH210-14 MACH210-18 MACH210-24 6 MACH 210A - The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- sult your local sales office to confirm availability of specific valid combinations or to check on newly re- leased combinations ...
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... PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs. The MACH210A inputs and I/O pins have built-in pull-up resistors. While it is always a good design practice to tie unused pins high, the 210A pull-up resistors provide design security and stability in the event that unused pins are left disconnected ...
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... PCI Compliance The MACH210A-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH210A-7/10’s predictable timing ensures compliance with the PCI AC specifica- tions independent of the design. On the other hand, in ...
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Switch Matrix Figure 1. MACH210 PAL Block MACH210-7/10/12/15/20, Q-12/15/20 Output Enable Output ...
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... 0 Max (Note 3) OUT Outputs Open ( 5 MHz (Note 4) and I (or I and OZL IH OZH MACH210A-7 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 = 0 mA) ...
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... Transparent Input Latch to Output Latch Gate Test Conditions MHz OUT D-Type T-Type LOW HIGH D-Type T-Type D-Type ) CNT T-Type D-Type T-Type LOW HIGH MACH210A-7 (Com’l) Typ Unit = Min Max Unit 7.5 ns 5 ...
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... APR t Input, I/O, or Feedback to Output Enable EA t Input, I/O, or Feedback to Output Disable ER Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 12 MACH210A-7 (Com’l) -7 Min Max Unit 11 ...
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... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-10/12 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 135 Unit V ...
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... MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-10/12 (Com’l) Typ Unit = -10 -12 Min Max Min Max Unit 6 7 ...
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... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210A-10/12 (Com’l) -10 -12 Min Max Min ...
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... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210A-12/14 (Ind) ) Operating – + with +4 +5.5 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 135 Unit ...
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... MHz OUT D-Type T-Type LOW HIGH D-Type 1/( T-Type D-Type ) CNT T-Type 1/( D-Type T-Type LOW HIGH 1/( WICL WICH MACH210A-12/14 (Ind) Typ Unit = -12 -14 Min Max Min Max Unit ...
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... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 18 MACH210A-12/14 (Ind) -12 -14 Min Max Min Max ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . Supply Voltage with Respect to Ground ...
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CAPACITANCE (Note 1) Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description t Input, I/O, or Feedback to Combinatorial Output PD (Note 3) Setup Time ...
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SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description t Input Latch Gate Width LOW WIGL t Input, I/O, or Feedback to Output Through Transparent PDLL Input and Output Latches t Asynchronous Reset to Registered or ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature With Power Applied . . . . . . . . . . . . . Supply Voltage with Respect to Ground ...
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CAPACITANCE (Note 1) Parameter Symbol Parameter Description CIN Input Capacitance COUT Output Capacitance SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description tPD Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, ...
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SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued) Parameter Symbol Parameter Description tAR Asynchronous Reset to Registered or Latched Output tARW Asynchronous Reset Width (Note 1) tARR Asynchronous Reset Recovery Time (Note 1) tAP Asynchronous Preset to Registered or ...
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... (Note 0 Max (Note 3) OUT MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-12 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 45 Unit ...
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... Test Conditions MHz OUT D-type T-type LOW HIGH D-type T-type D-type ) CNT T-type D-type T-type LOW HIGH MACH210AQ-12 (Com’l) Typ Unit = -12 Min Max Unit ...
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... EA t Input, I/O, or Feedback to Output Disable ER Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. MACH210AQ-12 (Com’l) -12 Min Max Unit ...
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... (Note 0 Max (Note 3) OUT 5V MHz CC A (Note 4) and I (or I and OZL IH OZH MACH210AQ-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 45 Unit ...
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... OUT D-type T-type LOW HIGH D-type 1/( T-type D-type ) CNT T-type D-type 1/( T-type D-type T-type LOW HIGH 1/( WICL WICH MACH210AQ-15/20 (Com’l) Typ Unit = -15 -20 Min Max Min Max Unit ...
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... Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. 30 MACH210AQ-15/20 (Com’l) -15 -20 Min Max Min ...
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... VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) MACH210AQ-18/24 (Ind – + ...
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... Test Conditions VIN = 2.0 V VCC = 5 VOUT = 2 MHz D-type T-type LOW HIGH D-type 1/(tS + tCO) T-type D-type T-type D-type 1/(tS + tH) T-type D-type T-type LOW HIGH 1/(tWICL + tWICH ) MACH210AQ-18/24 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 20 ...
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... Input, I/O, or Feedback to Output Disable (Note 3) Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit, for test conditions. 3. Parameters measured with 16 outputs switching. MACH210AQ-18/24 (Ind) -18 -24 Min Max Min ...
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TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS –1.0 34 (mA –0.8 –0.6 –0.4 –0 –20 –40 –60 –80 Output, LOW I (mA) OH ...
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... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register. MACH210AQ Frequency (MHz) MACH210-7/10/12/15/20, Q-12/15/20 MACH210A MACH210 80 90 100 14128I-8 35 ...
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TYPICAL THERMAL CHARACTERISTICS Measured ambient. These parameters are not tested. Parameter Symbol Parameter Description Thermal impedance, junction to case jc Thermal impedance, junction to ambient ja Thermal impedance, junction to jma ambient with air flow Plastic jc ...
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SWITCHING WAVEFORMS Input, I/O, or Combinatorial Input, I/O, or Feed- back t S Clock Registered Output Registered Output t WH Clock Clock Width Registered Input t SIR Input Register Clock Combinatorial Output Registered Input (MACH 2 and 4) Notes: 1. ...
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SWITCHING WAVEFORMS Latched In Gate Combinatorial Output Latched In Latched Out Input Latch Gate t IGS Output Latch Gate Notes 1 Input pulse amplitude 3 Input rise and fall ...
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SWITCHING WAVEFORMS t WICH Clock Input Register Clock Width (MACH 2 and 4) t ARW Input, I/O, or Feedback t AR Registered Output Clock Asynchronous Reset Input, I/O, or Feedback Notes 1 Input pulse ...
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KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUIT Specification Closed Open Closed Open Closed *Switching several outputs simultaneously should be avoided for ...
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PARAMETERS MAX The parameter f is the maximum clock rate at which MAX the device is guaranteed to operate. Because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, f three types of ...
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ENDURANCE CHARACTERISTICS The MACH families are manufactured using our advanced Electrically Erasable process. This technol- ogy uses an EE cell to replace the fuse link used in Endurance Characteristics Parameter Symbol Parameter Description Min Pattern Data Retention Time t DR ...
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INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection 1 k Input 100 k Preload Feedback Circuitry Input I/O MACH210-7/10/12/15/20, Q-12/15/ 100 14128I-25 43 ...
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POWER-UP RESET The MACH devices have been designed with the capa- bility to reset during system power-up. Following power- up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra ...
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USING PRELOAD AND OBSERVABILITY In order to be testable, a circuit must be both controllable and observable. To achieve this, the MACH devices incorporate register preload and observability. In preload mode, each flip-flop in the MACH device can be loaded ...
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PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches) .685 .695 .650 .656 Pin 1 I.D. .685 .695 .650 .656 .026 .050 REF .032 TOP VIEW 50 .062 .083 .042 .056 .009 .015 .165 .180 MACH210-7/10/12/15/20, Q-12/15/20 ...
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PHYSICAL DIMENSIONS* PQT044 44-Pin Thin Quad Flat Pack (measured in millimeters 0.95 1.05 0.30 0.45 1.00 REF. *For reference only. BSC is an ANSI standard for Basic Space Centering. 9.80 10.20 9.80 10.20 11.80 12.20 11 – 13 ...