SM5838AS Nippon Precision Circuits Inc, SM5838AS Datasheet - Page 12

• Manufacturer Part Number: SM5838AS
• Description: 5120 X 8-bit Synchronous FIFO
• Manufacturer: Nippon Precision Circuits Inc

1/2n data reduction (n
Screen resolution reduction, or 2
can be realized by combining both 1/2 data reduction
and 1/2 line extraction schemes. Furthermore, n
pixel reduction (for integer n) can be realized by
changing the WE and RE disable intervals and the
RW and RR reset timing.
2
2
DOUT
DOUT
2 pixel reduction (1/4 reduction)
CLK
2 pixel reduction (mosaic)
DIN
RW
CLK
WE
2 pixels
2 pixels
DIN
OE
RW
RR
RE
WE
OE
RR
RE
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0
Invalid
0
Valid
Valid
2 pixels
2 pixels
2
nH-2H
nH-1H
nH-1H
Invalid
Invalid
4
2
6
n pixel reduction)
909
909
908*
909
nH-2H
909
2 pixel reduction,
*Output date 902 to 908 forms the preceding 1H data.
0 1
0 1
0
2 3 4 5
2 3 4 5
2
nH-2H
nH
nH
4
SM5838AS
n
908
908
909
909
Also, if the same data is repeatedly read out in place
of other data that has been discarded, the screen reso-
lution can be reduced without changing the data rate
to realize a mosaic filter function.
0 1 2 3 4 5
0 1 2 3 4 5
0
0
2
nH+1H
nH+1H
nH
4
2
6
NIPPON PRECISION CIRCUITS—12
908*
909
909
nH
0 1
0 1
0
2 3 4 5
2 3 4 5
2
nH+2H
nH+2H
nH
4
908
908
909
909