SM5838AS Nippon Precision Circuits Inc, SM5838AS Datasheet - Page 11

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SM5838AS

Manufacturer Part Number
SM5838AS
Description
5120 X 8-bit Synchronous FIFO
Manufacturer
Nippon Precision Circuits Inc
Datasheet
1/2 Data Reduction
Input data rate reduction by half can be realized by
taking WE and RE simultaneously HIGH only once
every two clock cycles.
Noninterlace-to-interlace conversions line extraction
can be realized by switching WE LOW/HIGH in line
units and RE LOW/HIGH in word units.
1/2 data reduction
1/2 line extraction (noninterlace-to-interlace conversion)
DOUT
DOUT
CLK
DIN
CLK
DIN
RW
RW
WE
WE
RE
OE
RR
OE
RR
RE
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0 1 2 3 4 5
0
0
2
1
nH-1H
4
2
6
6
7 8 9
8
nH-1H
909
nH-2H
nH
0 1
10
2 3 4 5
12
nH
14
SM5838AS
5119
5118
1819
909
5119
909
0 1 2
0 1 2
0 1 2 3 4 5
0 1 2 3 4 5
0
0
2
1
nH+1H
4
2
6
6
7 8 9
NIPPON PRECISION CIRCUITS—11
8
nH+1H
909
nH
nH
0 1
10
2 3 4 5
12
nH+2H
14
5118
909
5119
909

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