25C040 MicrochipTechnology, 25C040 Datasheet - Page 10

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25C040

Manufacturer Part Number
25C040
Description
4KSPIBusSerialEEPROM
Manufacturer
MicrochipTechnology
Datasheet

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25AA040/25LC040/25C040
3.7
The following protection has been implemented to pre-
vent inadvertent writes to the array:
• The write enable latch is reset on power-up.
• A write enable instruction must be issued to set
• After a byte write, page write, or status register
• CS must be set high after the proper number of
• Access to the array during an internal write cycle
• The write enable latch is reset when the WP pin is
TABLE 3-3:
DS21204A-page 10
the write enable latch.
write, the write enable latch is reset.
clock cycles to start an internal write cycle.
is ignored and programming is continued.
low.
High
High
Low
WP
Data Protection
WRITE PROTECT FUNCTIONALITY MATRIX
WEL
X
0
1
Protected Blocks
Protected
Protected
Protected
Preliminary
Unprotected Blocks
3.8
The 25xx040 powers on in the following state:
• The device is in low power standby mode (CS= 1).
• The write enable latch is reset.
• SO is in high impedance state.
• A low level on CS is required to enter active state.
.
Protected
Protected
Writable
Power On State
1997 Microchip Technology Inc.
Status Register
Protected
Protected
Writable

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