D7225G NEC, D7225G Datasheet - Page 16

• Manufacturer Part Number: D7225G
• Description: Search -----> UPD7225G
• Manufacturer: NEC

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16
All bits of each address are effective. After the data is written, the data pointer points to address n + 4.
The segment decoder output written to the data memory corresponds to segments (a to n, DP) shown in Figure
2-2 as follows:
All contents of the 32
to high. In this case, if the DISPLAY ON command has been set, the contents of the display data latch are
converted to the segment drive signal in 32-bit units in synchronization with COM0-COM3 signals, and output
from the segment pins.
The figure below shows the relationship of the data memory, segment pins, and common signal selection
timing.
The data pointer (5 bits) specifies the address (0-31) of the data memory to which the display data will be
written (at the same time, the data pointer specifies the blinking data memory address (0-31)). The LOAD
DATA POINTER command is used to set the address to the data pointer (the data pointer can be initialized by
setting the /CS to low). When the data pointer is counted up to 31, it then becomes 0 at the next count, and
thus it repeats the operation shown below.
It should be noted that, if display data is written sequentially from address 0 in the divide-by-3 time division
mode, addresses 30 and 31 will not be written. However, if the data is written in the divide-by-3 time division
mode again, data will be written from addresses 30, 31, followed by 0 so that the display data previously written
to address 0 will be modified.
Figure 2-5. Data Memory, Segment Pins, and Common Signal Selection Timing
m
COM 0
COM 1
COM 2
COM 3
l
n + 3
j
4-bit data memory are transferred to the 32
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
g
0
1
2
DP
3
c
n + 2
Data Sheet S14308EJ6V0DS00
4
b
5
0
6
a
7
Address
8
d
9 10
e
n + 1
31
f
4-bit display data latch when the /CS is set
0
S28 S29 S30 S31
28 29 30 31
n
Address n
k
0
1
2
3
i
Bit
h
PD7225