TS256MDOM40V-S Transcend Information. Inc., TS256MDOM40V-S Datasheet - Page 6

• Manufacturer Part Number: TS256MDOM40V-S
• Description: Transcend 40-pin Ide Flash Module
• Manufacturer: Transcend Information. Inc.

Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below
Transcend Information Inc.
True IDE PIO Mode Read/Write Timing
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RD
6Z
2i
A
B
C
0
1
2
2
3
4
5
6
7
8
9
(1) t
(2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is
(3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is
120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD
high is 0 nsec, but minimum -IORD width shall still be met.
(4) t
(5) IORDY is not supported in this mode.
command recovery time or command inactive time. The actual cycle time equals the sum of the actual
command active time and the actual command inactive time. The three timing requirements of t0, t
t
a host implementation can lengthen either or both t
value reported in the device’s identify device data.
released by the device.
inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device
is not driving IORDY negated at t
applicable. If the device is driving IORDY negated at the time t
then t
Cycle time (min)
Address Valid to -IORD/-IOWR setup (min)
-IORD/-IOWR (min)
-IORD/-IOWR (min) Register (8 bit)
-IORD/-IOWR recovery time (min)
-IOWR data setup (min)
-IOWR data hold (min)
-IORD data setup (min)
-IORD data hold (min)
-IORD data tristate (max)
Address valid to IOCS16 assertion (max)
Address valid to IOCS16 released (max)
-IORD/-IOWR to address valid hold
Read Data Valid to IORDY active (min), if
IORDY initially low after tA
IORDY Setup time
IORDY Pulse Width (max)
IORDY assertion to release (max)
2i
T
T
T
0
shall be met. The minimum total cycle time requirement is greater than the sum of t
7
is the minimum total cycle time, t
r
r
r
and t
a
a
a
RD
n
n
n
shall be met and t5 is not applicable.
8
s
s
s
T
apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
T
T
c
c
c
S
S
S
e
e
e
1
n
1
n
1
n
2
2
d
2
1
d
d
8
8
8
3
Item
1
4
4
4
M
M
M
0
0
0
-
-
-
~
~
~
2
P
P
P
i
1
1
i
1
i
n
n
n
6
6
6
A
G
G
I
I
G
I
after the activation of -IORD or -IOWR, then t
D
D
D
D
D
2
D
E
E
E
is the minimum command active time, and t
O
O
O
F
F
F
M
M
M
4
4
l
l
l
a
a
a
4
4
4
s
s
s
0
Mode
1250
0
0
165
290
600
h
6
h
60
30
50
30
90
60
20
35
70
h
--
V
5
0
5
V
0
V
M
-
2
M
-
-
M
S
S
or t
S
o
o
o
Mode
1250
2i
125
290
383
d
d
50
45
20
35
30
50
45
15
35
d
--
5
0
5
1
to ensure that t
u
u
u
l
l
l
e
e
e
A
Mode
1250
after the activation of -IORD or -IOWR,
100
290
240
30
15
20
30
40
30
10
35
30
--
5
0
5
2
Mode
1250
0
N/A
N/A
180
80
80
70
30
10
20
30
10
35
30
is equal to or greater than the
3
5
0
5
5
shall be met and t
2i
Mode
1250
N/A
N/A
120
70
70
25
20
10
20
30
10
35
25
is the minimum
4
5
0
5
2
and t
Mode
N/A
N/A
N/A
N/A
N/A
2i
100
65
65
25
20
15
20
10
15
. This means
5
5
5
0
5
5
5
RD
Ver 1.2
Mode
N/A
N/A
N/A
N/A
N/A
2
is not
55
55
20
15
10
20
10
80
10
, and
6
5
5
0
5
5
5