AD6426 Analog Devices, AD6426 Datasheet - Page 8
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AD6426
Manufacturer Part Number
AD6426
Description
Enhanced GSM Processor
Manufacturer
Analog Devices
Datasheet
1.AD6426.pdf
(50 pages)
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A feature of the GSM system is the application, as part of the
TRANSMIT process, of data encryption for the purpose of link
security. After the INTERLEAVE module the data may be
encrypted using the prescribed A5/1 or A5/2 encryption
algorithm.
The RECEIVE function requires unmodulated baseband data
from the equalizer. As necessary the data is decrypted and
written to the DEINTERLEAVE module. This is conducted at
TDMA frame rate, although precise timing is not necessary at
this stage.
The DECODING process reads data from the
DEINTERLEAVE module, inverting the interleave algorithm
and decodes the error control codes, correcting and flagging
errors as appropriate. The data also includes a measure of
confidence expressed as two additional bits per received
symbol. These are used in the convolution decoder to improve
the error decoding performance. The resultant data is then
presented to the original sources as determined by the control
programming. The Channel Codec interfaces with the speech
transcoder for speech traffic data and with an equalizer for
recovered receive data. In the AD6426 the equalizer and
speech transcoder are implemented in the DSP.
Processor Sub-System
The Processor Sub-System consists of a high performance 16-
bit microcontroller together with a selection of peripheral
elements. The processor is a version of the Hitachi H8/300H
that has been developed to support GSM applications and
which is well suited to support the Protocol Stack and
Application Layer software.
DSP Sub-System
The DSP Sub-System consists of a high performance 16-bit
digital signal processor (DSP) with integrated RAM and ROM
memories. The DSP performs two major tasks: speech
transcoding and channel equalization. Additionally several
support functions are performed by the DSP. The instruction
code, which advises the DSP to perform these tasks, is stored
in the internal ROM. The DSP sub-system is completely self-
contained, no external memory or user-programming is
necessary.
Speech Transcoding
In Full Rate mode the DSP receives the speech data stream
from the EVBC and encodes the data from 104 kbit/s to 13
kbit/s. The algorithm used is Regular Pulse Excitation, with
Long Term Prediction (RPE-LTP) as specified in the 06-series
GSM Recommendations.
In Enhanced Full Rate mode, the DSP encodes the 104 kbit/s
speech data into 12.2 kbit/s (speech) +0.8 kbit/s (CRC and
repetition bits) as additionally specified in the Phase 2 version
of the 06-series GSM Recommendations. In both modes, the
DSP also performs the appropriate voice activity detection and
discontinuous transmission (VAD/DTX) functions.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
Preliminary Technical Information
- 8 -
Alternatively the DSP receives encoded speech data from the
channel codec sub-system including the Bad Frame Indicator
(BFI). The Speech decoder supports a Comfort Noise Insertion
(CNI) function that inserts a predefined silence descriptor into
the decoding process. The resulting data, at 104 kbit/s, is
transferred to the EVBC.
Equalization
The Equalizer recovers and demodulates the received signal
and establishes local timing and frequency references for the
mobile terminal as well as RSSI calculation. The equalization
algorithm is a version of the Maximum Likelihood Sequence
Estimation (MLSE) using the Viterbi algorithm. Two
confidence bits per symbol provide additional information
about the accuracy of each decision to the channel codec’s
convolutional decoder. The equalizer outputs a sequence of
bits including the confidence bits to the channel codec sub-
system.
Audio Control
The DSP subsystem is also responsible for the control of the
audio path. The EVBC provides two audio inputs and two
audio outputs, as well as a separate buzzer output, which are
switched and controlled by the DSP. Furthermore the EVBC
provides for variable gain and sensitivity which is also
controlled by the DSP under command of the Layer 1
software.
Tone Generation
All alert signals are generated by the DSP and output to the
EVBC. These alerts can be used for the buzzer or for the
earpiece. The tones used for alert signals can be fully defined
by the user by means of a description which provides all the
parameters required such as frequency content and duration of
components of the tone. The tone descriptions are provided by
the Layer 1 software.
Automatic Frequency Control (AFC)
The detection of the frequency correction burst provides the
frequency offset between the mobile terminal and the received
signal. This measure is supplied to the Layer 1 software which
then requests a correction of the master clock oscillator
frequency via the AFC-DAC in the EVBC. In order to do so
the Layer 1 software includes a transfer function for the
oscillator frequency against the voltage applied. The DSP
provides the measurements for the AFC.
Automatic Gain Control (AGC)
The DSP is also responsible for making measurements of the
power in the received signal. This is used for a number of
functions including RSSI measurement, adjacent channel
monitoring and AGC. The Layer 1 software passes the
requested gain level to the DSP, which then analyzes the
received signal and generates an AGC control signal.
Depending on the radio architecture, this control signal will be
used in digital form or, converted by the AD6425 in analog
form.
Confidential Information
AD6426