AD640 Analog Devices, AD640 Datasheet - Page 3

• Manufacturer Part Number: AD640
• Description: DC-Coupled Demodulating 120 MHz Logarithmic Amplifier
• Manufacturer: Analog Devices

AC SPECIFICATIONS
Model
Parameter
SIGNAL INPUTS (Pins 1, 20)
3 dB BANDWIDTH
LOGARITHMIC OUTPUTS
AC LINEARITY
PACKAGE OPTION
NUMBER OF TRANSISTORS
NOTES
10
11
12
13
All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate
outgoing quality levels.
Specifications subject to change without notice.
REV. C
1
2
3
4
5
6
7
8
9
Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50
For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50
Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
Logarithms to base 10 are used throughout. The response is independent of the sign of V
Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/ C.
Overall gain is trimmed using a 200 V square wave at 2 kHz, corrected for the onset of compression.
The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured
The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG
The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
Operating in circuit of Figure 24 using 0.1% accurate values for R
Essentially independent of supply voltages.
by linear regression over central region of transfer function.
V
for dual AD640 system.
Input Capacitance
Noise Spectral Density
Tangential Sensitivity
Each Stage
All Five Stages
Slope Current, I
Intercept, Dual AD640s
–40 dBm to –2 dBm
–35 dBm to –10 dBm
–75 dBm to 0 dBm
–70 dBm to –10 dBm
–75 dBm to +15 dBm
20-Lead Ceramic DIP Package (D)
20-Terminal Ceramic LCC (E)
20-Lead Plastic DIP Package (N)
20-Lead Plastic Leaded Chip Carrier (P)
IN
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
f< = 1 MHz
f = 30 MHz
f = 60 MHz
f = 90 MHz
f = 120 MHz
>3 mV dc, and over the full input range in ac applications.
Y
10
12
12
10
13
10, 11
5
20-Lead Ceramic DIP Package (D-20)
20-Terminal Ceramic LCC (E-20A)
20-Lead Plastic DIP Package (N-20)
20-Lead Plastic Leaded Chip Carrier (P-20A)
(V
S
=
Conditions
Either Pin to COM
1 kHz to 10 MHz
BW = 100 MHz
Pins 1 & 20 to 10 & 11
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 10 kHz
5 V, T
A
= +25 C, unless otherwise noted)
THERMAL CHARACTERISTICS
LA
Min
0.96
0.88
0.82
–90.6
and R
AD640]N
LB.
AD640JP
AD640J
Typ
2
2
–72
350
145
1.0
0.94
0.90
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
0.5
0.25
0.75
0.5
0.5
155
Includes slope and nonlinearity errors. Input offset errors also included for
–3–
10
(V
X
/1 V).
Max
1.04
1.00
0.98
–86.6
2.0
1.0
3.0
2.0
3.0
IN
.
Min
0.98
0.91
0.86
–89.6
25
25
24
28
AD640BD
AD640BE
JC
AD640B
AD640BP
= 223 mV rms.
Typ
2
2
–72
350
145
1.0
0.94
0.90
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
0.5
0.25
0.75
0.5
0.5
155
( C/W)
= 223 mV rms.
Max
–87.6
1.02
0.97
0.94
1.0
0.5
1.5
1.0
1.5
85
85
61
75
JA
( C/W)
Min
0.98
0.91
0.86
–89.6
AD640TE
AD640TD
AD640T
Typ
2
2
–72
350
145
1.0
0.94
0.90
0.88
0.85
–88.6
–87.6
–86.3
–83.9
–80.3
0.5
0.25
0.75
0.5
0.5
155
Max
1.02
0.97
0.94
–87.6
1.0
0.5
1.5
1.0
1.5
AD640
Units
pF
nV/ Hz
dBm
MHz
MHz
mA
mA
mA
mA
mA
dBm
dBm
dBm
dBm
dBm
dB
dB
dB
dB
dB