ISL6420 Intersil Corporation, ISL6420 Datasheet - Page 14

• Manufacturer Part Number: ISL6420
• Description: Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
• Manufacturer: Intersil Corporation

Feedback Compensation
Figure 14 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(Vout) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output filter
(L
The modulator transfer function is the small-signal transfer
function of Vout/V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage DV
Modulator Break Frequency Equations
F
F
FIGURE 14. VOLTAGE - MODE BUCK CONVERTER
LC
ESR
O
∆V
and C
=
OSC
=
-------------------------------------- -
2π
-------------------------------------------- -
2π
OSC
•
O
•
).
L
(
COMPARATOR
1
ESR C
O
COMPENSATION DESIGN
ERROR
AMP
V
ISL6420
1
•
E/A
DETAILED COMPENSATION COMPONENTS
PWM
C
E/A
•
O
Z
+
-
COMP
+
FB
-
C1
LC
. This function is dominated by a DC
O
)
REFERENCE
and a zero at F
C2
+
-
O
R2
DRIVER
DRIVER
14
Z
REF
and C
IN
E/A
Z
) is compared with the
FB
OSC
FB
O
V
), with a double pole
IN
PHASE
ESR
.
C3
(PARASITIC)
Z
IN
. The DC Gain of
L
IN
O
R1
) divided by the
R3
IN
ESR
C
V
at the
O
OUT
V
(EQ. 4)
(EQ. 5)
OUT
ISL6420
The compensation network consists of the error amplifier
(internal to the ISL6420) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 14. Use these guidelines for
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 15 shows an asymptotic plot of the DC-DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak do to the high Q factor of the output
filter and is not shown in Figure 15. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 15 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
F
F
F
F
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Z1
P1
Z2
P2
o
(~75% F
=
. The equations below relate the compensation
=
=
=
FB
----------------------------------
2π R3 C3
----------------------------------
2π R
----------------------------------------------------- -
2π
------------------------------------------------------ -
2π R2
. The goal of the compensation network is to provide
•
•
•
•
(
ST
ND
ST
ND
0dB
1
R1
1
LC
2 C1
•
•
Zero Below Filter’s Double Pole
Pole at the ESR Zero
•
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
)
) and adequate phase margin. Phase margin
+
1
1


R3
C1 C2
--------------------- -
C1
) C3
+
•
•
C2


0dB
(EQ. 6)
(EQ. 7)
(EQ. 8)
(EQ. 9)
P2
IN
and