ISL6420 Intersil Corporation, ISL6420 Datasheet
ISL6420
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ISL6420 Summary of contents
Page 1
... ENSS pin to ground sets a fully adjustable PWM soft start. Pulling the ENSS pin LOW disables the controller. The ISL6420 monitors the output voltage and generates a PGOOD (power good) signal when soft start sequence is complete and the output is within regulation. A built-in over voltage protection circuit prevents the output voltage from going above typically 115% of the set point ...
Page 2
... Pinout ISL6420 (QFN) TOP VIEW GPIO2 1 GPIO1 2 OCSET 3 BYPASS 4 VMSET Functional Block Diagram SGND SS FB COMP GPIO1/REFIN GPIO2 REFOUT VOLTAGE MARGINING VMSET/MODE 2 ISL6420 Ordering Information PART NUMBER ISL6420IR ISL6420IR-T 16 ISL6420IRZ 15 PGND (See Note) 14 CDEL ISL6420IRZ-T (See Note) ...
Page 3
... ENSS RT PGOOD C7 R2 0.1µF CDEL C8 SGND Typical 12V Input DC-DC Application Schematic 12V C1 C2 ENSS RT PGOOD R2 C7 CDEL C8 SGND ISL6420 C3 C4 PVCC VCC5 OCSET MONITOR AND PROTECTION BOOT UGATE OSC PHASE REF LGATE - - + + + + PGND - - COMP GPIO1/REFIN C11 GPIO2 R6 REFOUT ...
Page 4
... CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS Typical 12V Input DC-DC Application Schematic 12V C1 C2 VIN SS/EN RT CDEL R2 C7 PGOOD SGND CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS 4 ISL6420 PVCC VCC5 R1 OCSET MONITOR AND PROTECTION BOOT Q1 UGATE OSC PHASE LGATE - - + ...
Page 5
... Maximum Duty Cycle Minimum Duty Cycle FB pin bias current Undervoltage Protection Overvoltage Protection 5 ISL6420 Thermal Information Thermal Resistance (Typical) QFN Package (Notes Maximum Junction Temperature (Plastic Package 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Ambient Temperature Range -40°C to 85°C (for “I” suffix) Junction Temperature Range -40° ...
Page 6
... POWER GOOD AND CONTROL FUNCTIONS Power-Good Lower Threshold Power-Good Higher Threshold PGOOD Leakage Current PGOOD Voltage Low PGOOD Delay CDEL Current for PGOOD CDEL Threshold 6 ISL6420 SYMBOL TEST CONDITIONS RT = VCC5 -40°C to 85° -40°C to 85°C, with freq. set by A ...
Page 7
... VCC5 pin will be used input, the internal LDO regulator is disabled and the VIN must be connected to the VCC5. In both cases the PVCC pin should always be connected to VCC5 pin. (Refer to the Pin Descriptions sections for more details.) 7. Guaranteed by design. Not production tested. 7 ISL6420 SYMBOL TEST CONDITIONS VMSET/MODE = H, C ...
Page 8
... Typical Performance Curves 0.604 0.602 0.6 0.598 0.596 0.594 -40 -15 10 TEMPERATURE (°C) FIGURE 1. VREF vs TEMPERATURE 1.15 1.05 0.95 0.85 -40 -15 10 TEMPERATURE (°C) FIGURE 3. IOCSET vs TEMPERATURE FIGURE 5. PWM WAVEFORMS 8 ISL6420 320 310 300 290 280 270 FIGURE 4. EFFICIENCY vs LOAD CURRENT (VOUT = 3.3V) ...
Page 9
... Connecting this pin directly to VCC5 will select the oscillator free running frequency of 300kHz. By placing a resistor from this pin to GND, the oscillator frequency can be programmed from 100kHz to 1.4MHz. Figure 7 shows the oscillator frequency vs the RT resistance. 9 ISL6420 1400 1300 1200 1100 1000 900 ...
Page 10
... No Voltage Margining. Normal operation with internal reference. Buffered V = 0.6V. REFOUT No Voltage Margining. External reference. Buffered V = REFOUT V REFIN 10 ISL6420 TABLE 2. VOLTAGE MARGINING CONTROLLED BY GPIO1 PIN CONFIGURATIONS REFOUT GPIO1/REFIN Connect a 1µF Serves as a general capacitor for purpose I/O. Refer to bypass of external Table 2 reference. Connect a 1µF ...
Page 11
... R OCSET presence of switching noise on the input voltage. Voltage Margining The ISL6420 has a voltage margining mode that can be used for system testing. The voltage margining percentage is resistor selectable up to ±10%. The voltage margining mode can be enabled by connecting a margining set resistor ...
Page 12
... VMSET/MODE to VCC5. In this mode the chip can be configured to work with an external reference input and provide a buffered reference output. 12 ISL6420 If VMSET/MODE pin and the GPIO1/REFIN pin are both tied to VCC5, then the internal 0.6V reference is used as the error amplifier non-inverting input. The buffered reference output on REFOUT will be 0.6V ± ...
Page 13
... O Locate the ISL6420 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6420 must be sized to handle peak current. Figure 13 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown ...
Page 14
... ESR ISL6420 The compensation network consists of the error amplifier IN (internal to the ISL6420) and the impedance networks Z and closed loop transfer function with the highest 0dB crossing OUT frequency (f PHASE the difference between the closed loop phase at f ...
Page 15
... Given a sufficiently fast control loop design, the ISL6420 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
Page 16
... These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse- recovery of the lower MOSFETs body diode. The gate-charge losses are dissipated by the ISL6420 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, t MOSFET switching losses. Ensure that both MOSFETs are ...
Page 17
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 ISL6420 L20.4x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE C) ...