ISL12025 Intersil Corporation, ISL12025 Datasheet - Page 2

• Manufacturer Part Number: ISL12025
• Description: Real-Time Clock/Calendar
• Manufacturer: Intersil Corporation

Block Diagram
Pin Descriptions
SOIC
1
2
3
4
5
6
7
8
PIN NUMBER
SCL
SDA
32.768kHz
TSSOP
RESET
3
4
5
6
7
8
1
2
Interface
Decoder
Serial
X1
X2
SYMBOL
RESET
V
GND
SDA
SCL
V
X1
X2
BAT
Control
Decode
DD
8
Logic
2
The X1 pin is the input of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal. X1 can also be driven directly from a 32.768kHz source.
The X2 pin is the output of an inverting amplifier and is intended to be connected to one pin of an external
32.768kHz quartz crystal.
RESET. This is a reset signal output. This signal notifies a host processor that the “watchdog” time period
has expired or that the voltage has dropped below a fixed V
output. Recommended value for the pull-up resistor is 5kΩ, If unused, connect to ground.
Ground.
Serial Data (SDA) is a bidirectional pin used to transfer serial data into and out of the device. It has an
open drain output and may be wire OR’ed with other open drain or open collector outputs.
The Serial Clock (SCL) input is used to clock all serial data into and out of the device. The input buffer on
this pin is always active (not gated).
This input provides a backup supply voltage to the device. V
that the V
Power Supply.
(EEPROM)
Registers
Control/
Oscillator
OSC Compensation
DD
supply fails. This pin should be tied to ground if not used.
Watchdog
Timer
Frequency
Divider
Registers
(SRAM)
ISL12025
Status
Low Voltage
Reset
1Hz
Calendar
Alarm
BRIEF DESCRIPTION
Timer
Logic
Compare
EEPROM
Alarm Regs
(EEPROM)
ARRAY
Registers
Keeping
(SRAM)
4k
Time
TRIP
BAT
supplies power to the device in the event
threshold. It is an open drain active LOW
Circuitry
Battery
Switch
V
V
DD
BAT
October 18, 2006
FN6371.1