ISL12025 Intersil Corporation, ISL12025 Datasheet - Page 13

• Manufacturer Part Number: ISL12025
• Description: Real-Time Clock/Calendar
• Manufacturer: Intersil Corporation

A range from -30ppm to +30ppm can be represented by
using the three bits previously explained.
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in Battery Backup Mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in Battery
Backup Mode by setting this bit to “0” (default is “0”). See
“Power Control Operation” on page 14.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
options.
Option 1. Standard: Set “BSW = 0”
Option 2. Legacy /Default Mode: Set “BSW = 1”
See “Power Control Operation” on page 14 for more details.
Also see “I
LVR Operation” on page 23 for important details.
VTS2, VTS1, VTS0: V
The ISL12025 is shipped with a default V
(V
a non-volatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a non-volatile write, this
value will not change over normal operating and storage
conditions. However, ISL12025 has four (4) additional
selectable levels to fit the customers application. Levels are:
4.64V (default), 4.38V, 3.09V, 2.92V and 2.63V. The V
selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 5.
Care should be taken when changing the V
bits. If the V
the device will go into RESET and unless V
the device will no longer be able to communicate using the
I
2
C bus.
RESET
DTR2
0
0
0
0
1
1
1
1
DTR REGISTER
) per the ordering information table. This register is
TABLE 4. DIGITAL TRIMMING REGISTERS
2
RESET
C Communications During Battery Backup and
DTR1
0
1
0
1
0
1
0
1
voltage selected is higher than V
DD
DTR0
and Back Up Battery. There are two
RESET
0
0
1
1
0
0
1
1
13
Select Bits
ESTIMATED FREQUENCY
DD
RESET
DD
PPM
+10
+20
+30
threshold
-10
-20
-30
0
0
is increased,
select
DD
RESET
, then
ISL12025
Unique ID Registers
There are eight register bytes for storing the device ID.
(Address 0020h to 0027h). Each device contains these
bytes to provide a unique 64-bit ID programmed and tested
in the factory before shipment. These registers are read-
only, intended for serialization of end equipment, and cannot
be changed or overwritten.
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a non-volatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
much shorter cycle time (t = t
have no effect. The RWEL bit is reset by the completion of a
write to the CCR, so the sequence must be repeated to
again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an
incorrect number of bits or sending a start instead of a stop,
for example) the RWEL bit is not reset and the device
remains in an active mode. Writing all zeros to the status
register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event and trigger some action
as a result. The host can be notified by polling the Status
Register (SR) Alarm bits. These two volatile bits (AL1 for
1. Write a 02h to the Status Register to set the Write Enable
2. Write a 06h to the Status Register to set both the Register
VTS2
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
0
0
0
0
1
VTS1
0
0
1
1
0
VTS0
TABLE 5.
0
1
0
1
0
BUF
). Writes to undefined areas
V
4.64V
4.38V
3.09V
2.92V
2.63V
RESET
October 18, 2006
FN6371.1