EMC6D102 SMSC Corporation, EMC6D102 Datasheet - Page 81

• Manufacturer Part Number: EMC6D102
• Description: Fan Control Device
• Manufacturer: SMSC Corporation

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
SMSC EMC6D102
Fsmb
Tsp
Tbuf
Thd:sta
Tsu:sta
Tsu:sto
Thd:dat
Tsu:dat
Tlow
Thigh
Tf
Tr
C
SYMBOL
b
Note 9.5
Note 9.6
Note 9.7
SMB Operating Frequency
Spike Suppression
Bus free time between Stop and Start
Condition
Hold time after (Repeated) Start Condition.
After this period, the first clock is
generated.
Repeated Start Condition setup time
Stop Condition setup time
Data hold time
Data setup time
Clock low period
Clock high period
Clock/Data Fall Time
Clock/Data Rise Time
Capacitive load for each bus line
The SMBus timing (e.g., max clock frequency of 400kHz) specified exceeds that specified
in the System Management Bus Specification, Rev 1.1. This corresponds to the maximum
clock frequency for fast mode devices on the I
version 2.0, Dec. 1998.
At 400kHz, spikes of a maximum pulse width of 50ns must be suppressed by the input
filter.
If using 100 kHz clock frequency, the next data bit output to the SDA line will be 1250 ns
(1000 ns (T
PARAMETER
R
max) + 250 ns (T
DATASHEET
81
SU
:
DAT
10
1.3
0.6
0.6
0.6
0.3
100
1.3
0.6
20+0.1C
20+0.1C
min) @ 100 kHz) before the SCLK line is released.
MIN
LIMITS
b
b
2
C bus. See “The I
400
50
0.9
300
300
400
MAX
kHz
ns
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
pF
UNITS
2
C Bus Specification,”
Revision 0.4 (06-15-06)
Note 9.5
Note 9.6
Note 9.7
COMMENTS