EMC6D102 SMSC Corporation, EMC6D102 Datasheet - Page 68

• Manufacturer Part Number: EMC6D102
• Description: Fan Control Device
• Manufacturer: SMSC Corporation

Revision 0.4 (06-15-06)
7.2.27
AVG2
Register
Address
7Ch
0
0
0
1
SFTR[7:5]
AVG1
Read/
X
Write
0
0
1
R/W
Register 7Ch: Special Function Register
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
This register contains the following bits:
Bit[0] Low-Power Mode Select
0= Sleep Mode (default)
1= Shutdown Mode
Bit[1] Monitoring Mode Select
0= Continuous Monitor Mode (default)
1= Cycle Monitor Mode
Bit[2] INT# Enable
0=Disables INT# pin output function (default)
1=Enables INT# pin output function
Bit[3] SMSC Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted
results.
Bit [4] SMSC Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause
unwanted results.
Bits [7:5]
The AVG[2:0] bits determine the amount of averaging for each of the six measurements that are
performed by the hardware monitor before the reading registers are updated (TABLE 22). The
AVG[2:0] bits are priority encoded where the most significant bit has highest priority. For example,
when the AVG2 bit is asserted, 32 averages will be performed for each measurement before the
reading registers are updated regardless of the state of the AVG[1:0] bits.
Note: The default for the AVG[2:0] bits is ‘010’b.
AVG0
Special Function
Register Name
X
X
0
1
AVG[2:0]
REM DIODE 1
128
16
16
32
(MSb)
AVG2
Bit 7
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Table 7.17 AVG[2:0] Bit Decoder
REM DIODE 2
AVG1
Bit 6
128
DATASHEET
16
16
32
AVG0
Bit 5
AVERAGES PER READING
68
INTERNAL DIODE
SMSC
Bit 4
16
32
8
1
SMSC
Bit 3
(+2.5V, +5V, +12V, VCCP, AND VCC)
INTEN
Bit 2
ALL VOLTAGE READINGS
MONMD
Bit 1
16
32
8
1
SMSC EMC6D102
LPMD
(LSb)
Bit 0
Datasheet
Default
Value
40h