EMC6D102 SMSC Corporation, EMC6D102 Datasheet - Page 54

• Manufacturer Part Number: EMC6D102
• Description: Fan Control Device
• Manufacturer: SMSC Corporation

Revision 0.4 (06-15-06)
7.2.10
Register
Address
41h
Note
Read/
Write
Note: There is a start-up time of up to 82ms for monitoring after the start bit is set to ‘1’, during which
The following summarizes the operation of the part based on the Start bit:
1. If Start bit = '0' then:
s. Fans are set to Full On.
t.
u. No Status bits are set.
2. If Start bit = '1'
v. All fan control and monitoring will be based on the current values in the registers. There is no need
w. Status bits may be set.
x. Setting the START bit to 1 does not prevent the limit and parameter registers from being written.
Note: Once programmed, the register values will be saved when start bit is reset to ‘0’.
Register 41h: Interrupt Status Register 1
Note 7.9
Note: The individual enable bits for D2, AMB, and D1 are located in the Interrupt Enable 3 (Temp)
The Interrupt Status Register 1 bits are automatically set by the device, if enabled, whenever the 2.5V,
Vccp, 3.3V, or 5V input voltages violate the limits set in the limit and parameter registers or when the
measured temperature violates the limits set in the limit and parameter registers for any of the three
thermal inputs.
This register holds a bit set until the event is read by software or until the individual enable bit is
cleared (see Note below). The contents of this register are cleared (set to 0) automatically by the
EMC6D102 after it is read by software, if the voltage or temperature no longer violates the limits set
in the limit and parameter registers. Once set, the Interrupt Status Register 1 bits remain set until a
read event occurs or until the individual enable bits is cleared, even if the voltage or temperature no
longer violate the limits set in the limit and parameter registers. Note that clearing the group Temp,
Fan, or Volt enable bits or the global INTEN enable bit has no effect on the status bits. See
44-4Dh: Voltage Limit Registers on page 57
This register contains a bit that indicates that a bit is set in the other interrupt status register. If bit 7
is set, then a status bit is set in the Interrupt Status Register 2. Therefore, S/W can poll this register,
and only if bit 7 is set does the other register need to be read. This bit is cleared (set to 0) automatically
by the device if there are no bits set in Interrupt Status Registers 2.
This register is read only – a write to this register has no effect.
Note: Clearing the individual enable bits:
(See
R-C
7.9)
No voltage, temperature, or fan tach monitoring is performed. The values in the reading registers
will be N/A (Not Applicable), which means these values will not be considered valid readings until
the Start bit = '1'. The exception to this is the Tachometer reading registers, which always give the
actual reading on the TACH pins.
to preserve the default values after software has programmed these registers because no
monitoring or auto fan control will be done when Start bit = '0'.
time the reading registers are not valid.
register at offset 82h. The individual enable bits for 5V, VCC, Vccp, and 2.5V are located in
the Interrupt Enable 1 register at offset 7Eh.
This register is cleared on a read if no events are active.
Interrupt Status 1
Register Name
Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
DATASHEET
(MSb)
Bit 7
INT2
54
Bit 6
and
D2
on page
Bit 5
AMB
Bit 4
57.
D1
Bit 3
5V
Bit 2
VCC
Vccp
Bit 1
SMSC EMC6D102
(LSb)
Bit 0
2.5V
Datasheet
Registers
Default
Value
00h