TS128MEP6100 Transcend Information, TS128MEP6100 Datasheet - Page 8

• Manufacturer Part Number: TS128MEP6100
• Description: 128MB 90PIN PC133 CL3 SDRAM
• Manufacturer: Transcend Information

SIMPLIFIED TRUTH TABLE
TS128MEP6100
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power
Down Mode
SDQM
No Operation Command
Note:
Transcend information Inc.
COMMAND
1. OP Code: Operand Code
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. SBA
5. During burst read or write with auto precharge, new read/write command cannot be issued.
6. Burst stop command is valid at every burst length.
7. SDQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write SDQM latency is 0),
SA
A new command can be issued after 2 CLK cycles of MRS.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
If both SBA
If both SBA
If both SBA
If both SBA
If SA
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read SDQM latency is 2)
0
~SA
0
10
~SBA
/AP is “High” at row precharge, SBA
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
All Banks
Entry
Exit
Entry
Exit
11
, SBA
1
0
0
0
0
: Bank select address.
and SBA
and SBA
is “Low” and SBA
is “High” and SBA
0
~SBA
Entry
Exit
1
1
1
are “Low” at read, write, row active and precharge, bank A is selected.
are “High” at read, write, row active and precharge, bank D is selected.
: Program keys. (@MRS)
1
1
is “High” at read, write, row active and precharge, bank B is selected.
is “Low” at read, write, row active and precharge, bank C is selected.
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
L
L
L
0
and SBA
CKEn
X
H
H
X
X
X
X
X
H
H
X
L
L
L
1
/CS
are ignored and both banks are selected.
H
H
X
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
/RAS
8
H
X
H
H
H
X
V
X
X
H
X
V
X
X
H
L
L
L
L
/CAS
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
/WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
DQM
SO-DIMM With 16M X 16 3.3VOLT
128MB 90PIN PC133 CL3 SDRAM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
BA
V
V
V
V
X
0,1
A
10
H
H
H
L
L
L
/AP
OP CODE
Row Address
X
X
X
X
X
X
X
A
A
Address
Address
Column
(A
Column
(A
11
0
0
0
X
~A
~A
~A
,A
9
9
12
9
)
)
Note
4, 5
4, 5
1,2
3
3
3
3
4
4
6
7