MT8941 Mitel Networks Corporation, MT8941 Datasheet - Page 6

• Manufacturer Part Number: MT8941
• Description: CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
• Manufacturer: Mitel Networks Corporation

MT8941
The operation of DPLL #2 in SINGLE CLOCK-1
mode is identical to SINGLE CLOCK-2 mode,
providing the CEPT and ST-BUS compatible timing
signals synchro-nized to the internal 8 kHz signal
obtained from DPLL#1 in DIVIDE mode.
SINGLE CLOCK-1 mode is selected for DPLL #2, it
automatically selects the DIVIDE-1 mode for DPLL
#1, and thus, an external 1.544 MHz clock signal
applied at CVb (pin 21) is divided by DPLL #1 to
generate the internal signal at 8 kHz on to which
DPLL #2 locks. Similarly when SINGLE CLOCK-2
mode is selected, DPLL #1 is in DIVIDE-2 mode,
with an external signal of 2.048 MHz providing the
internal 8 kHz signal to DPLL #2.
modes, this internal signal is available on C8Kb (pin
3-48
Mode
10
12
13
14
15
11
0
1
2
3
4
5
6
7
8
9
#
M
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
M
S
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
M
S
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
CMOS
M
S
3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NORMAL MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the input
frame pulse (F0i).
NORMAL MODE
NORMAL MODE
NORMAL MODE
DIVIDE-1 MODE
DIVIDE-1 MODE
DIVIDE-1 MODE
DIVIDE-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.
NORMAL MODE
NORMAL MODE
NORMAL MODE
NORMAL MODE
DIVIDE-2 MODE
DIVIDE-2 MODE
DIVIDE-2 MODE
DIVIDE-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.
Table 4. Summary of Modes of Operation - DPLL #1 and #2
In both these
DPLL #1
When
Operating Modes
10) and DPLL #2 locks to the falling edge to provide
the CEPT and ST-BUS compatible timing signals.
This is in contrast to the Normal mode where these
timing signals are synchronized with the falling edge
of the 8 kHz signal on C8Kb.
Minor modes of DPLL #2
The minor modes for DPLL #2 depends upon the
status of the mode select bits MS2 and MS3 (pins 7
and 17).
Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the ST-
BUS clock at 2.048 MHz.
NORMAL MODE:
F0b is an input but has no function in this mode.
External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.
NORMAL MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).
Same as mode ‘0’.
SINGLE CLOCK-1 MODE
F0b is an input but has no function in this mode.
Same as mode 2.
SINGLE CLOCK-1 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
Same as mode ‘0’.
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
Same as mode 2.
FREE-RUN MODE:
Provides the ST-BUS timing signals with no
external inputs except the master clock.
Same as mode ‘0’.
SINGLE CLOCK-2 MODE:
F0b is an input but has no function in this mode.
Same as mode 2.
SINGLE CLOCK-2 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
DPLL #2