MT8941 Mitel Networks Corporation, MT8941 Datasheet - Page 11

• Manufacturer Part Number: MT8941
• Description: CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
• Manufacturer: Mitel Networks Corporation

At the slave end of the link (Figure 10) both the
DPLLs are in NORMAL mode, with DPLL #2
providing the ST-BUS timing signals locked to the 8
kHz frame pulse (E8Ko) extracted from the received
signal on the T1 line. The regenerated frame pulse
is looped back to DPLL #1 to provide the T1 line
clock, which is the same as the master end.
The 12.352 MHz and 16.384 MHz crystal clock
sources are necessary for DPLL #1 and #2,
respectively.
Crystal Clock
Crystal Clock
(16.384 MHz)
Crystal Clock
(16.384 MHz)
(12.352 MHz)
Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link
Figure 10 - Synchronization at the Slave End of the T1 Transmission Link
MS0
MS1
MS2
MS3
F0i
C12i
EN
C8Kb
C16i
EN
EN
V
SS
CV
C4o
C2o
MS0
MS1
MS2
MS3
F0i
C12i
EN
C8Kb
C16i
EN
EN
V
C
SS
MT8941
CV
C4o
C2o
RST
C
MT8941
RST
V
C4b
C2o
F0b
DD
Y
R
o
V
CVb
C4b
C2o
F0b
DD
R
V
DD
V
DD
Synchronization and Timing Signals for the
CEPT Transmission Link
The MT8941 can be used to provide the timing and
synchronization signals for the MH89790/790B,
Mitel’s CEPT (30+2) Digital Trunk Interface Hybrid.
Since the operational frequencies of the ST-BUS and
the CEPT primary multiplex digital trunk are the
same, only DPLL #2 is required.
DPLL #1 - NOT USED
DPLL #2 - FREE-RUN
C2i
F0i
DPLL #1 - NORMAL ( MS1=0)
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
MH89790B
C1.5i
C2i
F0i
E8Ko
MH89760B
Mode of Operation for the MT8941
Mode of Operation for the MT8941
OUTA
OUTB
DSTo
CSTi0
CSTi1
CSTo
DSTi
RxR
RxT
DSTo
CSTo
DSTi
CSTi
RxR
TxR
RxT
TxT
TRANSMIT
RECEIVE
TRANSMIT
RECEIVE
(MS0=1; MS1=0; MS2=1; MS3=1)
CMOS
MULTIPLEX
MT8980/81
(1.544 Mbps)
PRIMARY
SWITCH
ST-BUS
DIGITAL
MT8980/81
MT8941
SWITCH
CEPT
ST-BUS
LINK
LINK
T1
3-53