MT8941 Mitel Networks Corporation, MT8941 Datasheet - Page 2

• Manufacturer Part Number: MT8941
• Description: CMOS ST-BUS FAMILY Advanced T1/CEPT Digital Trunk PLL
• Manufacturer: Mitel Networks Corporation

MT8941
Pin Description
3-44
DIP
10
12
11
1
2
3
4
5
6
7
8
9
Pin #
PLCC
10
12
13
14
11
1
2
3
6
7
8
9
ENC4o
EN
Name
ENVC
EN
C8Kb Clock 8 kHz Bidirectional (TTL compatible input and Totem-pole output) - This is the 8
C8Kb
MS0
C12i
MS1
MS2
C16i
C4o
F0b
V
F0i
MS0
C12i
MS1
MS2
C16i
VSS
C4o
F0b
SS
F0i
C4o
CV
CMOS
Variable clock enable (TTL compatible input) - This input directly controls the three states
of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts
it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1
is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high
impedance state. However, if MS1 is HIGH, CVb is always an input.
Mode select ‘0’ input (TTL compatible) - This input in conjunction with MS1 (pin 4) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
12.352 MHz Clock input (TTL compatible) - Master clock input for DPLL #1.
Mode select-1 input (TTL compatible) - This input in conjunction with MS0 (pin 2) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)
Frame pulse input (TTL compatible) - This is the frame pulse input at 8 kHz. DPLL #1
locks to the falling edge of this input to generate T1 (1.544 MHz) clock.
Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending
on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as
an input to an external frame pulse.
Mode select-2 input (TTL compatible) - This input in conjunction with MS3 (pin 17) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)
16.384 MHz Clock input (TTL compatible) - Master clock input for DPLL #2.
Enable 4.096 MHz clock (TTL compatible input) - This active high input enables C4o (pin
11) output. When LOW, the output C4o is in high impedance condition.
kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mode.
When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal
provided by DPLL #1 which is also connected internally to DPLL #2.
Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).
Ground (0 Volt)
10
11
12
1
2
3
4
5
6
7
8
9
24 PIN PDIP
24
23
22
21
20
19
18
17
16
15
14
13
VDD
RST
CV
CVb
Yo
Bi
Ai
MS3
ENC2o
C2o
C2o
C4b
Figure 2 - Pin Connections
Description
ENC4o
MS1
MS2
C16i
F0b
NC
F0i
5
6
7
8
9
10
11
28 PIN PLCC
25
24
23
22
21
20
19
NC
CVb
Yo
Bi
Ai
MS3
ENC2o