MT9V403 Micron, MT9V403 Datasheet - Page 13

• Manufacturer Part Number: MT9V403
• Description: 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
• Manufacturer: Micron

Serial Bus Description
through the two-wire serial interface bus. The
MT9V403 is a two-wire serial interface slave with
device ID "1011100x" and is controlled by the two-wire
serial interface clock (SCLK), which is driven by the
two-wire serial interface master. Data is transferred
into and out through the two-wire serial interface data
(SDATA) line. The SDATA line is pulled up to 3.3V off-
chip by a 1.5KΩ resistor. Either the slave or master
device can pull the SDATA line down—the two-wire
serial interface protocol determines which device is
allowed to pull the SDATA line down at any given time.
Protocol
eral different transmission codes, as follows:
• a start bit
• the slave device eight-bit address
• a(n) (no) acknowledge bit
• an eight-bit message
• a stop bit
Sequence
ter sending a start bit. After the start bit, the master
sends the slave device's eight-bit address. The last bit
of the address determines if the request will be a read
or a write, where a “0” indicates a write (i.e., address
B8h) and a “1” indicates a read (i.e., address B9h). The
slave device acknowledges its address by sending an
acknowledge bit back to the master.
the eight-bit register address to which a write should
take place. The slave sends an acknowledge bit to indi-
cate that the register address has been received. The
master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight-
bits. The MT9V403 uses a 16-bit data for its internal
registers, thus requiring two eight-bit transfers to write
to one register. To write/read this 16-bit data, first per-
form a write/read the eight MSBs, then perform
another write/read for eight LSBs. After 16 bits are
transferred, the register address should be incre-
mented, so that the next 16 bits are written to the next
register address. The master stops writing by sending a
start or stop bit.
the master sends the write-mode slave address and
eight-bit register address, just as in the write request.
The master then sends a start bit and the read-mode
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Registers are written to and read from the MT9V403
The two-wire serial host interface bus defines sev-
A typical read or write sequence begins by the mas-
If the request was a write, the master then transfers
A typical read sequence is executed as follows. First
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
13
slave address. The master then clocks out the register
data eight bits at a time. The master sends an acknowl-
edge bit after each eight-bit transfer. The register
address should be incremented after every 16 bits is
transferred. The data transfer is stopped when the
master sends a no-acknowledge bit.
Bus Idle State
are HIGH. Control of the bus is initiated with a start
bit, and the bus is released with a stop bit. Only the
master can generate the start and stop bits.
Start Bit
of the data line while the clock line is HIGH.
Stop Bit
of the data line while the clock line is HIGH.
Slave Address
device consists of seven bits of address and one bit of
direction. A “0” in the LSB of the address indicates
write mode, and a “1” indicates read mode.
Data Bit Transfer
The two-wire serial interface clock pulse is provided by
the master. The data must be stable during the HIGH
period of the two-wire serial interface clock—it can
only change when the two-wire serial interface clock is
LOW. Data is transferred eight bits at a time, followed
by an acknowledge bit.
Acknowledge Bit
The transmitter (which is the master when writing, or
the slave when reading) releases the data line, and the
receiver indicates an acknowledge bit by pulling the
data line LOW during the acknowledge clock pulse.
No-Acknowledge Bit
line is not pulled down by the receiver during the
acknowledge clock pulse. A no-acknowledge bit is
used to terminate a read sequence.
The bus is idle when both the data and clock lines
The start bit is defined as a HIGH-to-LOW transition
The stop bit is defined as a LOW-to-HIGH transition
The eight-bit address of a two-wire serial interface
One data bit is transferred during each clock pulse.
The master generates the acknowledge clock pulse.
The no-acknowledge bit is generated when the data
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©2004 Micron Technology. Inc.