MT9V012 Micron, MT9V012 Datasheet - Page 11

• Manufacturer Part Number: MT9V012
• Description: 1/6-Inch VGA CMOS Digital Image Sensor
• Manufacturer: Micron

Output Data Timing (Default Mode)
Figure 8: Pixel Data Timing Example
Figure 9: Row Timing and FRAME_VALID/LINE_VALID Signals
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
LINE_VALID
D
OUT
PIXCLK
[9:0]
Blanking
The MT9V012 output data is synchronized with the PIXCLK output. When LINE_VALID
is HIGH, one pixel datum is output on the 10-bit D
default, the PIXCLK signal runs at one-half the frequency of the master clock, CLKIN,
and its rising edges occur one-half of a master clock period after transitions on
LINE_VALID, FRAME_VALID, and D
a clock to sample the data. PIXCLK is continuously enabled, even during the blanking
period. The MT9V012 can be programmed to delay the PIXCLK edge relative to the D
transitions from 0 to 3.5 master clocks, in steps of one-half of a master clock. This can be
achieved by programming the corresponding bits in Reg0x0A. The parameters P, A, and
Q in Figure 9 are defined in Table 3 on page 12.
P
Number of master clocks
0 [9:0]
FRAME_VALID
P
LINE_VALID
1 [9:0]
P
2 [9:0]
MT9V012 - 1/6-Inch VGA CMOS Digital Image Sensor
P
P
Valid Image Data
3 [9:0]
11
A
Q
OUT
P
4 [9:0]
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(see Figure 8). This allows PIXCLK to be used as
Output Data Format (Default Mode)
P
5
A
P
n-2
OUT
Q
P
n-1 [9:0]
output every PIXCLK period. By
A
P
©2004 Micron Technology, Inc. All rights reserved.
P
n [9:0]
Blanking
Preliminary
OUT
‡