MT9M019 Aptina Imaging Corporation, MT9M019 Datasheet - Page 6

• Manufacturer Part Number: MT9M019
• Description: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
• Manufacturer: Aptina Imaging Corporation

Functional Overview
Figure 1:
PDF: 7723845879/Source:2828556980
MT9M019 DS - Rev. F 5/10 EN
Block Diagram
The MT9M019 is a progressive-scan sensor that generates a stream of pixel data at a
constant frame rate. It uses an on-chip, phase-locked loop (PLL) to generate all internal
clocks from a single master input clock running between 6 and 27 MHz. The maximum
pixel rate is 64 Mp/s, corresponding to a system clock rate of 64 MHz. A block diagram of
the sensor is shown in Figure 1.
The core of the sensor is a 1.3Mp active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row in turn. In
the time interval between resetting a row and reading that row, the pixels in the row inte-
grate incident light. The exposure is controlled by varying the time interval between
reset and readout. Once a row has been read, the data from the columns is sequenced
through an analog signal chain (providing offset correction and gain), and then through
an ADC. The output from the ADC is a 10-bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain (which provides further data
path corrections and applies digital gain).
The pixel array contains optically active and light-shielded (“dark”) pixels. The dark
pixels are used to provide data for on-chip offset-correction algorithms (“black level”
control).
The sensor contains a set of control and status registers that can be used to control many
aspects of the sensor behavior including the frame size, exposure, and gain setting.
These registers can be accessed through a two-wire serial interface.
The output from the sensor is a Bayer pattern; alternate rows are a sequence of either
green/red pixels or blue/green pixels. The offset and gain stages of the analog signal
chain provide per-color control of the pixel data.
The control registers, timing and control, and digital processing functions shown in
Figure 1 are partitioned into two logical parts:
• A sensor core that provides array control and data path corrections. The output of the
• Additional functionality is required to support the SMIA standard. This includes a
A flash output strobe is provided to allow an external xenon or LED light source to
synchronize with the sensor exposure time.
Sensor (APS)
Active-Pixel
sensor core is a serial CCP2-compliant pixel data stream.
horizontal and vertical image scaler, a limiter, a data compressor, an output FIFO, and
a serializer.
Analog Processing
Array
ADC
6
MT9M019: 1/5-Inch 1.3Mp CMOS Digital Image Sensor
Scaler
Control Registers
Timing Control
Limiter
FiFO
Aptina reserves the right to change products or specifications without notice.
Data
Out
©2006 Aptina Imaging Corporation. All rights reserved.
Signals
Two-wire
Serial Interface
Functional Overview
Sync
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