MT90826 Mitel Networks Corporation, MT90826 Datasheet - Page 4

• Manufacturer Part Number: MT90826
• Description: Quad Digital Switch
• Manufacturer: Mitel Networks Corporation

MT90826
4
Pin Description (continued)
Pin # MQFP
34
35
36
37
38
40
41
42
43
44
46
47
48
49
50
51
CMOS
Pin # PBGA
M11
M12
M13
N11
N12
N13
H11
K11
L11
L12
L13
K12
K10
J11
J12
K9
PLLGND
PLLVDD
RESET
Name
TRST
XTM1
XTM2
TMS
TDO
TCK
DT1
AT1
TDI
IC1
IC2
IC3
F0i
Test Mode Select (3.3V Input with Internal pull-up):
JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up
when not driven.
Test Serial Data In (3.3V Input with Internal pull-up):
JTAG serial test instructions and data are shifted in on
this pin. This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data Out (3.3V Output): JTAG serial data is
output on this pin on the falling edge of TCK. This pin is
held in high impedance state when JTAG scan is not
enabled.
Test Clock (5V Tolerant Input): Provides the clock to the
JTAG test logic.
Test Reset (3.3V Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by
putting it in the Test-Logic-Reset state. This pin is pulled
by an internal pull-up when not driven. This pin should be
pulsed low on power-up, or held low, to ensure that the
device is in the normal functional mode.
PLL Test Access 1 (3.3V Input): Use for PLL testing
only. No connect for normal operation.
PLL Test Access 1 (3.3V Input): Use for PLL testing
only. No connect for normal operation.
Internal Connection 1 (3.3V Input with internal pull-
down): Connect to V
Device Reset (5V Tolerant Input): This input (active
LOW) puts the device in its reset state which clears the
device internal counters and registers.
Internal Connection 2 (3.3V Input with internal pull-
down): Connect to V
When IC3 pin is tied to 3.3V, this pin is used as the PLL
bypass clock input for PLL testing only.
Internal Connection 3 (3.3V Input with internal pull-
down): Connect to V
When this pin is tied to 3.3V, it enables the PLL bypass
mode for PLL testing only.
Master Frame Pulse (5V Tolerant Input): This input
accepts a 60ns wide negative frame pulse.
Analog Test Access (Bidirectional): Use for PLL testing
only. No connect for normal operation.
Digital Test Access Output (Output): Use for PLL
testing only. No connect for normal operation.
Phase Lock Loop Ground.
Phase Lock Loop Power Supply: 3.3V
SS
SS
SS
Description
for normal operation.
for normal operation.
for normal operation.
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