MT90826 Mitel Networks Corporation, MT90826 Datasheet - Page 13

• Manufacturer Part Number: MT90826
• Description: Quad Digital Switch
• Manufacturer: Mitel Networks Corporation

Advanced Information
15-11
DR2
8-0
Bit
10
9
0
0
0
0
1
1
1
FE4
15
Read/Write Address:
Reset Value:
FE3
14
DR1
0
0
1
1
0
0
1
FD8-0
Name
FE4-0
CFE
FD9
FE2
13
Table 6 - Serial Data Rate Selections and External Clock Rates
FE1
12
DR0
0
1
0
1
0
1
0
Table 7 - Frame Alignment (FAR) Register Bits
FE0
11
Frame Evaluation Input Select. The binary value expressed in these bits
refers to the frame evaluation inputs, FEi0 to FEi31.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and FD9 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the control register is changed from 1
to 0.
Frame Delay Bit 9. The falling edge of FEi input is sampled during the internal
master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit
allows the measurement resolution to 1/2 internal master clock cycle.
See Figure 4 for clock signal alignment.
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB)
0001
0000
Internal Master Clock
CFE
10
Serial Interface Mode
H
H
,
.
C8i
C16i
C32i
16 and 8 Mb/s
4 and 8 Mb/s
2 and 4 Mb/s
FD9
9
16 Mb/s
8 Mb/s
4 Mb/s
2 Mb/s
FD8
8
FD7
7
8Mb/s, 16Mb/s, 4&8Mb/s, 16&8Mb/s
FD6
6
Operation Mode
Description
4Mb/s, 2&4Mb/s
2Mb/s
FD5
16.384MHz
16.384MHz
16.384MHz
(CPLL=0)
5
CLK
FD4
4
CMOS
FD3
3
FD2
2
16.384MHz
8.192MHz
8.192MHz
(CPLL=1)
MT90826
FD1
1
CLK
FD0
0
13