MT90826 Mitel Networks Corporation, MT90826 Datasheet - Page 10

• Manufacturer Part Number: MT90826
• Description: Quad Digital Switch
• Manufacturer: Mitel Networks Corporation

MT90826
10
1. Bit A13 must be high for access to data and connection memory positions. Bit A13 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4Mb/s
4. Channels 0 to 127 are used when serial stream is at 8Mb/s
5. Channels 0 to 255 are used when serial stream is at 16Mb/s
A13
A13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.
.
.
A12
A12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
.
.
.
A11
A11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
.
.
.
Stream Address (ST0-31)
CMOS
A10
A10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
.
.
.
Table 4 - Address Map for Memory Locations (A13 = 1)
A9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A9
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
.
.
.
Table 3 - Address Map for Registers (A13 = 0)
A8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A8
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
.
.
.
A7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
.
.
Stream 22
Stream 23
Stream 24
Stream 25
Stream 26
Stream 27
Stream 28
Stream 29
Stream 30
Stream 31
Location
Stream
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A7
A4
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
.
.
.
.
.
.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
A6
A3
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
.
.
.
.
.
.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
A5
A2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
.
.
.
.
.
.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
A4
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
.
.
.
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
Channel Address (Ch0-255)
A3
A0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
.
.
.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
A2
Control Register, CR
Frame Alignment Register, FAR
Input Offset Selection Register 0, DOS0
Input Offset Selection Register 1, DOS1
Input Offset Selection Register 2, DOS2
Input Offset Selection Register 3, DOS3
Input Offset Selection Register 4, DOS4
Input Offset Selection Register 5, DOS5
Input Offset Selection Register 6, DOS6
Input Offset Selection Register 7, DOS7
Frame Output Offset Register, FOR0
Frame Output Offset Register, FOR1
Frame Output Offset Register, FOR2
Frame Output Offset Register, FOR3
Unused
Unused
Unused
Bit Error Input Selection Register, BISR
Bit Error Count Register, BECR
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
.
.
.
Advanced Information
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
.
.
.
.
.
.
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
.
.
.
.
.
.
Location
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3)
Ch 64
Ch 65
.
Ch 126
Ch 127 (Note 4)
Ch 128
Ch 129
.
Ch 254
Ch 255 (Note 5)
Location
Channel