MT9074 Mitel Networks Corporation, MT9074 Datasheet - Page 30

• Manufacturer Part Number: MT9074
• Description: T1/E1/J1 Single Chip Transceiver
• Manufacturer: Mitel Networks Corporation

MT9074
channels from the write pointer, a slip will occur,
which will put the read pointer 28 channels from the
write pointer. This provides a worst case hysteresis
of 13 channels peak (26 channels peak-to-peak) or a
wander tolerance of 208 UI.
Framing Algorithm
Frame Alignment in T1 Mode
In T1 mode MT9074 will synchronize to DS1 lines
formatted with either the D4 or ESF protocol. In
either mode the framer maintains a running 3 bit
history of received data for each of the candidate bit
positions. Candidate bit positions whose incoming
patterns fail to match the predicted pattern (based on
the 3 bit history) are winnowed out. If, after a 10 bit
history has been examined, only one candidate bit
position remains within the framing bit period, the
receive side timebase is forced to align to that bit
position. If no candidates remain after a 10 bit
history, the process is re-initiated. If multiple
candidates exist after a 24 bit history timeout period,
the framer forces the receive side timebase to
synchronize to the next incoming valid candidate bit
position. In the event of a reframe, the framer starts
searching at the next bit position over. This prevents
persistent locking to a mimic as the controller may
initiate a software controlled reframe in the event of
locking to a mimic.
Under software control the framing criteria may be
tuned (see Framing Mode Select Register, page 1H,
address 10H). Selecting D4 framing invites a further
decision whether or not to include a cross check of
Fs bits along with the Ft bits. If Fs bits are checked
(by setting control bit CXC high - bit 5 of the Framing
Mode Select Word, page 1H, address 10H),
30
Read Pointer
47 CH
Read Pointer
60 CH
34 CH
512 Bit
Elastic
Store
Write Pointer
Figure 14 - Read and Write Pointers in the Slip Buffers
2 CH
28 CH
Read Pointer
Read Pointer
15 CH
-13 CH
13 CH
multiframer alignment is forced at the same time as
terminal frame alignment. If only Ft bits are checked,
multiframe alignment is forced separately, upon
detection of the Fs bit history of 00111 (for normal
D4 trunks) or 000111000111 (for SLC-96 trunks).
For D4 trunks, a reframe on the multiframe alignment
may be forced at any time without affecting terminal
frame alignment.
In ESF mode the circuit will optionally confirm the
CRC-6 bits before forcing a new frame alignment.
This is programmed by setting control bit CXC high
(bit 5 of the Framing Mode Select Word, page 1H,
address 10H). A CRC-6 confirmation adds a
minimum of 6 milliseconds to the reframe time. If no
CRC-6 match is found after 16 attempts, the framer
moves to the next valid candidate bit position
(assuming other bit positions contain a match to the
framing pattern) or re-initiates the whole framing
procedure (assuming no bit positions have been
found to match the framing pattern).
The framing circuit is off - line. During a reframe, the
rest of the circuit operates synchronous with the last
frame alignment. Until such time as a new frame
alignment is achieved, the signalling bits are frozen
in their states at the time that frame alignment was
lost, and error counting for Ft, Fs, ESF framing
pattern or CRC-6 bits is suspended.
Frame Alignment in E1 mode
In E1 mode MT9074 contains three distinct framing
algorithms:
multiframe
alignment. Figure 17 is a state diagram that
illustrates these algorithms and how they interact.
alignment
basic
frame
Advance Information
and
Wander Tolerance
alignment,
CRC-4
multiframe
signalling