MT58L64V36P Micron Semiconductor, MT58L64V36P Datasheet - Page 18

• Manufacturer Part Number: MT58L64V36P
• Description: (MT58LxxxxP) 2Mb SRAM
• Manufacturer: Micron Semiconductor

NOT RECOMENDED FOR NEW DESIGNS
READ/WRITE TIMING PARAMETERS
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_C.p65 – Rev. C, Pub. 11/02
BWa#-BWd#
SYMBOL
t
f
t
t
t
t
t
t
t
KC
KH
KQ
KQLZ
OELZ
OEHZ
AS
ADDRESS
KF
KL
(NOTE 4)
(NOTE 2)
ADSC#
ADSP#
BWE#,
ADV#
OE#
CLK
CE#
D
Q
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
is HIGH, CE2# is HIGH and CE2 is LOW.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
5.0
1.6
1.6
1.5
0
0
A1
-5
High-Z
High-Z
200
3.5
3.0
t ADSS
t CES
t AS
A2
6.0
1.7
1.7
1.5
1.5
Back-to-Back READs
0
t ADSH
t CEH
t KH
t AH
-6
t KC
t KQLZ
(NOTE 5)
Q(A1)
166
3.5
3.5
t KL
t KQ
7.5
1.9
1.9
1.5
1.5
0
-7.5
Q(A2)
133
4.0
4.0
t OEHZ
3.2
3.2
1.5
2.2
10
0
-10
t WS
Single WRITE
t DS
D(A3)
READ/WRITE TIMING
A3
100
5.0
4.5
t DH
t WH
MHz
ns
ns
ns
ns
ns
ns
ns
ns
A4
18
t OELZ
PIPELINED, SCD SYNCBURST SRAM
SYMBOL
t
t
t
t
t
t
t
t
t
ADSS
WS
DS
CES
AH
ADSH
WH
DH
CEH
2Mb: 128K x 18, 64K x 32/36
(NOTE 1)
Q(A4)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
BURST READ
-5
Q(A4+1)
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
Q(A4+2)
-6
1.5
Q(A4+3)
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
-7.5
DON’T CARE
©2002, Micron Technology, Inc.
D(A5)
2.2
2.2
2.2
2.2
0.5
0.5
0.5
0.5
0.5
A5
-10
Back-to-Back
WRITEs
UNDEFINED
D(A6)
A6
ns
ns
ns
ns
ns
ns
ns
ns
ns