MT58L64V36P Micron Semiconductor, MT58L64V36P Datasheet
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MT58L64V36P
Manufacturer Part Number
MT58L64V36P
Description
(MT58LxxxxP) 2Mb SRAM
Manufacturer
Micron Semiconductor
Datasheet
1.MT58L64V36P.pdf
(20 pages)
NOT RECOMENDED FOR NEW DESIGNS
2Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
• Separate +3.3V or +2.5V isolated output buffer
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 options available
OPTIONS
• Timing (Access/Cycle/MHz)
• Configurations
• Package
• Operating Temperature Range
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_C.p65 – Rev. C, Pub. 11/02
supply (V
WRITE
and address pipelining
I/Os and control signals
3.5ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
3.3V I/O
2.5V I/O
100-pin TQFP
Commercial (0°C to +70°C)
128K x 18
128K x 18
64K x 32
64K x 36
64K x 32
64K x 36
DD
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
Q)
MT58L128L18PT-10
Part Number Example:
®
BSRAM-compatible)
MT58L128V18P
MT58L128L18P
MT58L64V32P
MT58L64V36P
MT58L64L32P
MT58L64L36P
MARKING
None
-7.5
-10
™
-5
-6
T
DD
)
1
PIPELINED, SCD SYNCBURST SRAM
MT58L128L18P, MT58L64L32P, MT58L64L36P;
MT58L128V18P, MT58L64V32P, MT58L64V36P
3.3V V
Cycle Deselect
GENERAL DESCRIPTION
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
18, 64K x 32, or 64K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock
input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable (CE#),
two additional chip enables for easy depth expansion
(CE2, CE2#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BWx#), and global write
(GW#).
(OE#), clock (CLK), and snooze enable (ZZ). There is
also a burst mode pin (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one
to four bytes wide (x32/x36), as controlled by the write
control inputs.
status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance
pin (ADV#).
*JEDEC-standard MS-026 BHA (LQFP).
The Micron
Micron’s 2Mb SyncBurst SRAMs integrate a 128K x
Asynchronous inputs include the output enable
Burst operation can be initiated with either address
2Mb: 128K x 18, 64K x 32/36
DD
, 3.3V or 2.5V I/O, Pipelined, Single-
®
100-Pin TQFP*
SyncBurst
™
SRAM family employs
©2002, Micron Technology, Inc.