XC2C64 Xilinx, XC2C64 Datasheet - Page 7

• Manufacturer Part Number: XC2C64
• Description: (XC2C32 - XC2C512) Coolrunner-ii CPLD Family
• Manufacturer: Xilinx

pin through a macrocell. When the DataGATE rail is
asserted high, any pass transistor switch attached to it is
blocked. Note that each pin has the ability to attach to the
AIM through a DataGATE pass transistor, and thus be
blocked. A latch automatically captures the state of the pin
when it becomes blocked. The DataGATE Assertion Rail
threads throughout all possible I/Os, so each can participate
if chosen. Note that one macrocell is singled out to drive the
rail, and that macrocell is exposed to the outside world
DS090 (v1.7) October 2, 2003
Preliminary Product Specification
R
Figure 6: DataGATE Architecture (output drivers not shown)
Latch
Latch
To AIM
To AIM
MC16
MC16
MC1
MC2
MC1
MC2
PLA
PLA
DataGATE Assertion Rail
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AIM
through a pin, for inspection. If DataGATE is not needed,
this pin is an ordinary I/O.
Figure 5: CMOS I
PLA
PLA
I
CC
MC16
MC16
MC1
MC2
MC1
MC2
0
CC
To AIM
To AIM
To AIM
vs. Switching Frequency Curve
Frequency
Latch
Latch
Latch
CoolRunner-II CPLD Family
DS090_05_101001
DS090_06_111201
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