XC2C64 Xilinx, XC2C64 Datasheet - Page 3

• Manufacturer Part Number: XC2C64
• Description: (XC2C32 - XC2C512) Coolrunner-ii CPLD Family
• Manufacturer: Xilinx

Architecture Description
CoolRunner-II CPLD is a highly uniform family of fast, low
power CPLDs. The underlying architecture is a traditional
CPLD architecture combining macrocells into Function
Blocks (FBs) interconnected with a global routing matrix,
the Xilinx Advanced Interconnect Matrix (AIM). The Func-
tion Blocks use a Programmable Logic Array (PLA) config-
uration which allows all product tems to be routed and
shared among any of the macrocells of the FB. Design soft-
ware can efficiently synthesize and optimize logic that is
subsequently fit to the FBs and connected with the ability to
utilize a very high percentage of device resources. Design
changes are easily and automatically managed by the soft-
ware, which exploits the 100% routability of the Program-
mable Logic Array within each FB. This extremely robust
building block delivers the industry’s highest pinout reten-
DS090 (v1.7) October 2, 2003
Preliminary Product Specification
I/O Pin
I/O Pin
I/O Pin
JTAG
R
BSC and ISP
16
16
MC16
MC1
MC2
Fast Inputs
Figure 1: CoolRunner-II CPLD Architecture
Function
Block 1
PLA
16 FB
40
Clock and Control Signals
www.xilinx.com
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BSC Path
AIM
tion, under very broad design conditions. The architecture
will be explained by expanding the detail as we discuss the
underlying Function Blocks, logic and interconnect.
The design software automatically manages these device
resources so that users can express their designs using
completely generic constructs without knowledge of these
architectural details. More advanced users can take advan-
tage of these details to more thoroughly understand the
software’s choices and direct its results.
Figure 1
tion Blocks attach to pins and interconnect to each other
within the internal interconnect matrix. Each FB contains 16
macrocells. The BSC path is the JTAG Boundary Scan Con-
trol path. The BSC and ISP block has the JTAG controller
and In-System Programming Circuits.
16 FB
40
shows the high-level architecture whereby Func-
Function
Block n
PLA
Fast Inputs
MC16
MC1
MC2
CoolRunner-II CPLD Family
16
16
DS090_01_121201
I/O Pin
I/O Pin
I/O Pin
3