EPCS64 Altera Corporation, EPCS64 Datasheet - Page 7

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Figure 4–3. FPGA Configuration in AS Mode (Serial Configuration Device Programmed by APU or Third-Party
Programmer)
Notes to
(1)
(2)
(3)
Altera Corporation
July 2004
V
Serial configuration devices cannot be cascaded.
Connect the FPGA MSEL[] input pins to select the AS configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
CC
Figures 4–2
= 3.3-V.
Configuration
Device (2)
f
Serial
DATA
DCLK
and 4–3:
ASDI
nCS
Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
The FPGA acts as the configuration master in the configuration flow and
provides the clock to the serial configuration device. The FPGA enables
the serial configuration device by pulling the nCS signal low via the nCSO
signal (See
instructions and addresses to the serial configuration device via the ASDO
signal. The serial configuration device responds to the instructions by
sending the configuration data to the FPGA’s DATA0 pin on the falling
edge of DCLK. The data is latched into the FPGA on the DCLK signal’s
rising edge.
The FPGA controls the nSTATUS and CONF_DONE pins during
configuration in AS mode. If the CONF_DONE signal does not go high at
the end of configuration or if the signal goes high too early, the FPGA will
pulse its nSTATUS pin low to start reconfiguration. Upon successful
configuration, the FPGA releases the CONF_DONE pin, allowing the
external 10-kΩ resistor to pull this signal high. Initialization begins after
the CONF_DONE goes high. After initialization, the FPGA enters user
mode.
For more information on configuring Stratix II FPGAs in AS mode or
other configuration modes, see Configuring Stratix II Devices in the
Configuration Handbook.
10 kΩ
V
CC
(1)
10 kΩ
Core Version a.b.c variable
Figures 4–2
V
CC
(1) V
CC
10 kΩ
(1)
and 4–3). Subsequently, the FPGA sends the
CONF_DONE
nSTATUS
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
Cyclone Series FPGA
Stratix II or
Configuration Handbook, Volume 2
MSEL[n]
nCEO
n
(3)
N.C.
4–7