EPCS64 Altera Corporation, EPCS64 Datasheet - Page 24

• Manufacturer Part Number: EPCS64
• Description: (EPCS1 - EPCS64) Serial Configuration Devices
• Manufacturer: Altera Corporation

Timing Information
Timing
Information
Figure 4–16. Write Operation Timing
4–24
Configuration Handbook, Volume 2
DCLK
DATA
ASDI
nCS
t
NCSH
High Impedance
t
DSU
Bit n
parameter specifies the V
power mode and the I
is in stand-by power mode (see
Power-On Reset
During initial power-up, a POR delay occurs to ensure the system voltage
levels have stabilized. During AS configuration, the FPGA controls the
configuration and has a longer POR delay than the serial configuration
device. Therefore, the POR delay is governed by the Stratix II FPGA
(typically 12 ms or 100 ms) or Cyclone series FPGA (typically 100 ms).
Error Detection
During AS configuration with the serial configuration device, the FPGA
monitors the configuration status through the nSTATUS and CONF_DONE
pins. If an error condition occurs (nSTATUS drives low) or if the
CONF_DONE pin does not go high, the FPGA will initiate reconfiguration
by pulsing the nSTATUS and nCSO signals, which controls the chip select
pin on the serial configuration device (nCS).
After an error, configuration automatically restarts if the Auto-Restart
Upon Frame Error option is turned on in the Quartus II software. If the
option is turned off, the system must monitor the nSTATUS signal for
errors and then pulse the nCONFIG signal low to restart configuration.
Figure 4–16
configuration device.
t
NCSSU
t
DH
Core Version a.b.c variable
Bit n
shows the timing waveform for write operation to the serial
1
t
CH
CC0
parameter specifies the current when the device
CC
supply current when the device is in active
Table
t
CL
4–18).
Bit 0
t
CSH
Altera Corporation
July 2004