PIC24H Microchip Technology, PIC24H Datasheet - Page 57

• Manufacturer Part Number: PIC24H
• Description: Flash Programming Specification
• Manufacturer: Microchip Technology

5.3
As shown in Figure 5-4, entering ICSP Program/Verify
mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
PIC24H devices. There is no minimum time require-
ment for holding at V
val of at least P18 must elapse before presenting the
key sequence on PGD.
FIGURE 5-4:
5.4
5.4.1
Flash memory write and erase operations are controlled
by the NVMCON register. Programming is performed by
setting NVMCON to select the type of erase operation
(Table 5-2) or write operation (Table 5-3) and initiating
the programming by setting the WR control bit
(NVMCON<15>).
In ICSP mode, all programming operations are self-
timed. There is an internal delay between the user set-
ting the WR control bit and the automatic clearing of the
WR control bit when the programming operation is
complete. Please refer to Section TABLE 8-1: “AC/
DC Characteristics and Timing Requirements” for
information about the delays associated with various
programming operations.
© 2007 Microchip Technology Inc.
MCLR is briefly driven high then low.
A 32-bit key sequence is clocked into PGD.
MCLR is then driven high within a specified
period of time and held.
MCLR
V
PGD
PGC
DD
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Entering ICSP Mode
Flash Memory Programming in
ICSP Mode
PROGRAMMING OPERATIONS
IH
P6
ENTERING ICSP™ MODE
. After V
DD
in the case of dsPIC33F/
IH
P14
is removed, an inter-
P18
V
b31
IH
0
b30
1
Program/Verify Entry Code = 0x4D434851
Preliminary
b29
IH
0
,
b28
P1A
0
P1B
b27
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0001’
(more easily remembered as 0x4D434851 in hexa-
decimal). The device will enter Program/Verify mode only
if the sequence is valid. The Most Significant bit (MSb) of
the most significant nibble must be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time P19 and P7 must elapse before presenting
data on PGD. Signals appearing on PGD before P7
has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While
in ICSP mode, all unused I/Os are placed in the
high-impedance state.
1
TABLE 5-2:
0x404F
0x404D
0x404C
0x4042
0x4040
NVMCON
Value
...
b3
0
Erase all code memory, executive memory
and Configuration registers (does not
erase Unit ID or Device ID registers).
Erase General Segment and FGS
Configuration register.
Erase Secure Segment and FSS
Configuration register. This operation will
also erase the General Segment and FGS
Configuration register.
Erase a page of code memory or
executive memory.
Erase a Configuration register byte.
b2
0
NVMCON ERASE
OPERATIONS
b1
0
V
Erase Operation
IH
b0
1
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P19
DS70152D-page 57
P7
IH
must be