PIC24H Microchip Technology, PIC24H Datasheet - Page 34

• Manufacturer Part Number: PIC24H
• Description: Flash Programming Specification
• Manufacturer: Microchip Technology

dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
3.2
Before programming can begin, the programmer must
confirm that the programming executive is stored in
executive memory. The procedure for this task is
shown in Figure 3-2.
First, ICSP mode is entered. Then, the unique Applica-
tion ID Word stored in executive memory is read. If the
programming executive is resident, the Application ID
Word is 0xBB, which means programming can resume
as normal. However, if the Application ID Word is not
0xBB, the programming executive must be programmed
to executive code memory using the method described in
Section 6.0 “Programming the Programming Exec-
utive to Memory”.
Section 5.0 “Device Programming – ICSP” describes
the ICSP programming method. Section 5.11 “Reading
the Application ID Word” describes the procedure for
reading the Application ID Word in ICSP mode.
FIGURE 3-2:
DS70152D-page 34
Enter ICSP™ Mode
Resident in Memory
Prog. Executive is
Confirming the Presence of the
Programming Executive
Application ID
Application ID
from Address
Read the
0x807F0
0xBB?
Finish
Start
Is
Yes
CONFIRMING PRESENCE
OF PROGRAMMING
EXECUTIVE
No
Prog. Executive must
be Programmed
Preliminary
3.3
Program/Verify mode requires three steps:
1.
2.
3.
The programming voltage applied to MCLR is V
which is essentially V
PIC24H devices. There is no minimum time require-
ment for holding at V
val of at least P18 must elapse before presenting the
key sequence on PGD.
The key sequence is a specific 32-bit pattern,
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 0x4D434850 in hexa-
decimal format). The device will enter Program/Verify
mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
Once the key sequence is complete, V
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval
time of at least P19 and P7 must elapse before present-
ing data on PGD. Signals appearing on PGD before P7
has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
As shown in Figure 3-3, entering Enhanced ICSP
The MCLR pin is briefly driven high then low.
A 32-bit key sequence is clocked into PGD.
MCLR is then driven high within a specified
period of time and held.
Entering Enhanced ICSP Mode
IH
. After V
DD
© 2007 Microchip Technology Inc.
in the case of dsPIC33F/
IH
is removed, an inter-
www.DataSheet4U.com
IH
must be
IH
,