ISL12028 Intersil Corporation, ISL12028 Datasheet - Page 14

• Manufacturer Part Number: ISL12028
• Manufacturer: Intersil Corporation

For example, C
100000) = 4.5pF, and C
The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented by
using three bits above.
PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: - Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0”. (default is “0”). See
Reset and Power Control section.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
options.
Option 1. Standard Mode: Set “BSW = 0”
Option 2. Legacy/Default Mode: Set “BSW = 1”
See Power Control Operation later in this document for more
details. Also see “I
backup and LVR Operation” in the Applications section for
important details.
DTR2
0
0
0
0
1
1
1
1
DTR REGISTER
TABLE 5. DIGITAL TRIMMING REGISTERS
DTR1
LOAD
0
1
0
1
0
1
0
1
2
C Communications During Battery
(ATR = 00000) = 12.5pF, C
DD
LOAD
and Back Up Battery. There are two
DTR0
0
0
1
1
0
0
1
1
14
(ATR = 011111) = 20.25pF.
ESTIMATED FREQUENCY
PPM
+10
+20
+30
-10
-20
-30
0
0
LOAD
(ATR =
ISL12028
VTS2, VTS1, VTS0: V
The ISL12028 is shipped with a default V
(V
a non-volatile with no protection, therefore any writes to this
location can change the default value from that marked on
the package. If not changed with a non-volatile write, this
value will not change over normal operating and storage
conditions. However, ISL12028 has four (4) additional
selectable levels to fit the customers application. Levels are:
4.64V(default), 4.38V, 3.09V, 2.92V and 2.63V. The V
selection is via 3 bits (VTS2, VTS1 and VTS0). See Table 6
below.
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
Write all eight bytes to the RTC registers, or one byte to the
SR, or one to five bytes to the control registers. This
sequence starts with a start bit, requires a slave byte of
“11011110” and an address within the CCR and is terminated
by a stop bit. A write to the EEPROM registers in the CCR
will initiate a non-volatile write cycle and will take up to 20ms
to complete. A write to the RTC registers (SRAM) will require
much shorter cycle time (t = t
have no effect. The RWEL bit is reset by the completion of a
write to the CCR, so the sequence must be repeated to
again initiate another change to the CCR contents. If the
sequence is not completed for any reason (by sending an
incorrect number of bits or sending a start instead of a stop,
for example) the RWEL bit is not reset and the device
remains in an active mode. Writing all zeros to the status
register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
1. Write a 02h to the Status Register to set the Write Enable
2. Write a 06h to the Status Register to set both the Register
RESET
VTS2
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
0
0
0
0
1
) per the ordering information table. This register is
VTS1
0
0
1
1
0
RESET
VTS0
TABLE 6.
0
1
0
1
0
BUF
). Writes to undefined areas
Select Bits
DD
V
4.64V
4.38V
3.09V
2.92V
2.63V
RESET
threshold
April 17, 2006
RESET
FN8233.3