ISL12028 Intersil Corporation, ISL12028 Datasheet - Page 13

• Manufacturer Part Number: ISL12028
• Manufacturer: Intersil Corporation

BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
INT Register: Interrupt Control and
Frequency Output Register
IM, AL1E, AL0E - Interrupt Control and Status Bits
There are two Interrupt Control bits, Alarm 1 Interrupt Enable
(AL1E) and Alarm 0 Interrupt Enable (AL0E) to specifically
enable or disable the alarm interrupt signal output (IRQ/
F
AL0E or both bits are set to ‘1’ and both the FO1 and FO0
bits are set to 0 (F
The IM bit enables the pulsed interrupt mode. To enter this
mode, the AL0E or AL1E bits are set to “1”, and the IM bit to
“1”. The IRQ/F
alarm occurs. This means that once the interrupt mode
alarm is set, it will continue to alarm for each occurring
match of the alarm and present time. This mode is
convenient for hourly or daily hardware interrupts in
microcontroller applications such as security cameras or
utility meter reading.
In the case both Alarms are enabled.
FO1, FO0 - Programmable Frequency Output Bits
These are two output control bits. They select one of three
divisions of the internal oscillator, that is applied to the IRQ/
F
output. When using this function, the Alarm output function is
disabled.
OUT
OUT
0
0
0
0
1
1
1
1
). The interrupts are enabled when either the AL1E or
output pin. Table 4 shows the selection bits for this
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
OUT
PROTECTED ADDRESSES
OUT
output will now be pulsed each time an
disabled).
None (Default)
180
100
000
000
000
000
000
TABLE 3.
ISL12028
h
h
h
h
h
h
h
13
– 1FF
– 1FF
– 1FF
– 03F
– 07F
– 0FF
– 1FF
h
h
h
h
h
h
h
ARRAY LOCK
First 16 Pages
First 4 Pages
First 8 Pages
Upper 1/4
Upper 1/2
Full Array
Full Array
None
ISL12028
Oscillator Compensation Registers
There are two trimming options.
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64 to +110 ppm of total
adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34 to
+80ppm to the nominal frequency compensation.
The effective on-chip series load capacitance, C
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). C
controlled capacitors, C
and X2 pins to ground (see Figure 12). The value of C
C
The effective series load capacitance is the combination of
C
C
C LOAD
C X
X2
X1
LOAD
FO1
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
TABLE 4. PROGRAMMABLE FREQUENCY OUTPUT BITS
0
0
1
1
=
is given by the following formula:
and C
(
16 b5
=
=
⋅
FO0
---------------------------------- -




16 b5
---------------------------------------------------------------------------------------------------------------------------- -
X2
---------- -
C
0
1
0
1
1
X1
+
:
⋅
8 b4
X1
X2
1
+
FIGURE 12. DIAGRAM OF ATR
⋅
---------- -
C
+
1
8 b4
X2
LOAD
+
⋅
4 b3


C
C
X1
X2
⋅
+
X1
4 b3
is changed via two digitally
Alarm output (F
+
⋅
and C
2 b2
OUTPUT FREQUENCY
⋅
+
2 b2
2
+
⋅
X2
1 b1
32.768kHz
4096Hz
⋅
OSCILLATOR
, connected from the X1
+
1Hz
CRYSTAL
1 b1
+
OUT
⋅
0.5 b0
+
⋅
disabled)
0.5 b0
+
⋅
9
LOAD
)pF
+
April 17, 2006
9
 pF

,
X1
FN8233.3
and