74F899QC Fairchild Semiconductor, 74F899QC Datasheet - Page 2

• Manufacturer Part Number: 74F899QC
• Description: IC TXRX W/GEN&CHECKER 28-PLCC
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F899QC

• Logic Type: Transceiver, Non-Inverting
• Number Of Elements: 1
• Number Of Bits Per Element: 9
• Current - Output High, Low: 3mA, 64mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Input Loading/Fan-Out
Pin Descriptions
Functional Description
The 74F899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
• Bus A (B) communicates to Bus B (A), parity is gener-
ated and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B[0:7] (A[0:7]) can be checked
and monitored by ERRB (ERRA).
A
B
APAR, BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
A
B
APAR
BPAR
ODD/EVEN
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
0
0
Pin Names
Pin Names
–A
–B
0
0
–A
–B
7
7
7
7
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active LOW for EVEN Parity
Output Enables for A or B Bus, Active LOW
Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode
Latch Enables for A and B Latches, HIGH for Transparent Mode
Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs
Data Inputs/
Data Outputs
Data Inputs/
Data Outputs
A Bus Parity
Input/Output
B Bus Parity
Input/Output
Parity Select Input
Output Enable Inputs
Mode Select Input
Latch Enable Inputs
Error Signal Outputs
Description
2
• Bus A (B) communicates to Bus B (A) in a feed-through
• Independent Latch Enables (LEA and LEB) allow other
Description
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
permutations of generating/checking (see Function
Table).
HIGH/LOW
600/106.6
600/106.6
50/33.3
1.0/1.0
150/40
1.0/1.0
1.0/1.0
150/40
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
U.L.
HIGH/LOW
Output I
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
20 A/ 0.6 mA
12 mA/64 mA
12 mA/64 mA
Input I
3 mA/24 mA
3 mA/24 mA
1 mA/20 mA
IH
OH
/I
/I
IL
OL