74F899QC Fairchild Semiconductor, 74F899QC Datasheet

IC TXRX W/GEN&CHECKER 28-PLCC

74F899QC

Manufacturer Part Number
74F899QC
Description
IC TXRX W/GEN&CHECKER 28-PLCC
Manufacturer
Fairchild Semiconductor
Series
74Fr
Datasheet

Specifications of 74F899QC

Logic Type
Transceiver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
9
Current - Output High, Low
3mA, 64mA
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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© 1999 Fairchild Semiconductor Corporation
74F899SC
74F899QC
74F899
9-Bit Latchable Transceiver
with Parity Generator/Checker
General Description
The 74F899 is a 9-bit to 9-bit parity transceiver with trans-
parent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit
data busses in either direction. It has a guaranteed current
sinking capability of 24 mA at the A-bus and 64 mA at the
B-bus.
The 74F899 features independent latch enables for the
ODD/EVEN parity, and separate error signal output pins for
checking parity.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
A-to-B direction and the B-to-A direction, a select pin for
Order Number
Pin Assignment for SOIC
Package Number
M28B
V28A
28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
DS010195
Features
Logic Symbol
Latchable transceiver with output sink of 24 mA at the
A-bus and 64 mA at the B-bus
Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
Independent latch enables for A-to-B and B-to-A
directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
May be used in systems applications in place of the
74F543 and 74F280
May be used in system applications in place of the
74F657 and 74F373 (no need to change T/R to check
parity)
Package Description
Pin Assignment for PCC
February 1989
Revised August 1999
www.fairchildsemi.com

Related parts for 74F899QC

74F899QC Summary of contents

Page 1

... Package Number 74F899SC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F899QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Input Loading/Fan-Out Pin Names A –A Data Inputs Data Outputs B –B Data Inputs Data Outputs APAR A Bus Parity Input/Output BPAR B Bus Parity Input/Output Parity Select Input ODD/EVEN Output Enable Inputs GBA, GAB Mode ...

Page 3

Function Table Inputs GAB GBA SEL LEA LEB Busses A and B are 3-STATE Generates parity from B[0:7] based on O/E (Note 1). Generated parity Generated parity checked against BPAR ...

Page 4

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with V 0V) CC Standard ...

Page 5

DC Electrical Characteristics Symbol Parameter Min I Output Leakage IL I Current OZL I Output Short-Circuit Current OS I Bus Drainage Test ZZ I Power Supply Current CCH I Power Supply Current CCL I Power Supply Current CCZ AC Electrical ...

Page 6

AC Path A , APAR B , BPAR BPAR A , APAR BPAR n (B APAR ERRA n (B ERRB) n www.fairchildsemi.com FIGURE 1. FIGURE 2. FIGURE 3. 6 ...

Page 7

AC Path (Continued) O/E ERRA O/E ERRB O/E BPAR (O/E APAR) APAR ERRA (BPAR ERRB) FIGURE 4. FIGURE 5. FIGURE 6. 7 www.fairchildsemi.com ...

Page 8

AC Path (Continued) ZH, HZ ZL, LZ www.fairchildsemi.com FIGURE 7. FIGURE 8. FIGURE 9. 8 ...

Page 9

AC Path (Continued) SEL BPAR (SEL APAR) LEA BPAR, B[0:7] (LEB APAR, A[0:7]) TS(H), TH(H) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) FIGURE 10. FIGURE 11. FIGURE 12. 9 www.fairchildsemi.com ...

Page 10

AC Path (Continued) TS(L), TH(L) LEA APAR, A[0:7] (LEB BPAR, B[0:7]) www.fairchildsemi.com FIGURE 13. FIGURE 14. 10 ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B 11 www.fairchildsemi.com ...

Page 12

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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