ADC1175-50CIMT National Semiconductor, ADC1175-50CIMT Datasheet - Page 10

• Manufacturer Part Number: ADC1175-50CIMT
• Description: 8-Bit/ 50 MSPS/ 125 mW A/D Converter
• Manufacturer: National Semiconductor

www.national.com
Timing Diagram
Functional Description
The ADC1175-50 maintains superior dynamic performance
with input frequencies up to 1/2 the clock frequency, achiev-
ing 6.8 effective bits with a 50 MHz sampling rate and
25 MHz input frequency.
The analog signal at V
by V
Input voltages below V
sist of all zeroes. Input voltages above V
output word to consist of all ones. While the ADC1175-50 is
optimized for top and bottom reference voltages (V
V
mance at these values, V
log supply voltage, AV
4.0V. V
V
the clock frequency to maintain SINAD performance.
If V
are connected together, the nominal values of V
RB
RB
RT
) or 2.6V and 0.6V, respectively, and will give best perfor-
. With V
RT
and V
RT
and V
should always be at least 1.0V more positive than
RT
RTS
RB
voltages above 2.8V, it is necessary to reduce
are digitized to eight bits at up to 55 MSPS.
are connected together and V
IN
RB
DD
that is within the voltage range set
RT
, while V
will cause the output word to con-
has a range of 1.0V to the ana-
RB
has a range of 0V to
FIGURE 1. ADC1175-50 Timing Diagram
RT
will cause the
RB
FIGURE 2. t
RT
and V
and V
RT
and
RBS
RB
EN
, t
10
DIS
are 2.6V and 0.6V, respectively. If V
nected together and V
V
Data is acquired at the falling edge of the clock and the digi-
tal equivalent of that data is available at the digital outputs
2.5 clock cycles plus t
as long as the clock signal is present at pin 12.
The Power Down pin (PD), when high, puts the ADC1175-50
into a power down mode where power consumption is typi-
cally less than 5 mW. When the part is powered down, the
digital output pins are in a high impedance TRI-STATE. It
takes about 140 ns for the part to become active upon com-
ing out of the power down mode.
Applications Information
1.0 THE ANALOG INPUT
The analog input of the ADC1175-50 is a switch followed by
an integrator. The capacitance seen at the input changes
with the clock level, appearing as 4 pF when the clock is low,
Test Circuit
RT
DS100896-24
is 2.3V.
OD
RB
later. The ADC1175-50 will convert
is grounded, the nominal value of
RT
DS100896-23
and V
RTS
are con-