ADC1175-50CIMT National Semiconductor, ADC1175-50CIMT Datasheet
ADC1175-50CIMT
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ADC1175-50CIMT Summary of contents
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... Features n Internal Track-and-Hold function n Single +5V operation n Internal reference bias resistors Connection Diagram Ordering Information ADC1175-50CIJM ADC1175-50CIJMX ADC1175-50CIMT ADC1175-50CIMTX TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation n Industry standard pinout n Power-down mode ( Key Specifications n Resolution n Maximum Sampling Frequency ...
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Block Diagram Pin Descriptions and Equivalent Circuits Pin Symbol No RTS www.national.com Equivalent Circuit Analog signal input. Conversion range Reference Top Bias with internal pull ...
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... Bypass well if not grounded. See Section 2.0 for more information. CMOS/TTL compatible Digital input that, when high, puts the ADC1175-50 into a power-down mode where total power consumption is typically less than 5 mW. With this pin low, the device is in the normal operating mode. ...
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... AV have a common source and be separately bypassed with a 10 µF capacitor and a 0.1 µF ceramic chip capacitor. See Section 4.0 for more information. The ground return for the analog supply ADC1175-50 package. 4 Description and should be connected together close to the ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Input or Output Pin Reference Voltage ( CLK, PD Voltage Range Digital Output Voltage ( ...
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Converter Electrical Characteristics The following specifications apply for AV 50 MHz at 50% duty cycle. Boldface limits apply for T Symbol Parameter ANALOG INPUT AND REFERENCE CHARACTERISTICS V –V Self Bias Voltage Delta RTS RBS V –V Reference Voltage Differential ...
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... TTL load on each digital output. The values for maximum power dissipation listed above will be reached only when the ADC1175-50 is operated in a severe fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed) ...
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Typical Performance Characteristics INL Plot DS100896-11 DNL vs Temperature DS100896-14 SINAD & ENOB vs Temp & DS100896- Temperature OD DS100896-20 www.national.com = CLK DNL Plot DS100896-12 SNR vs Temp ...
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Specification Definitions ANALOG INPUT BANDWIDTH is a measure of the fre- quency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with f equal to 100 ...
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... Applications Information 1.0 THE ANALOG INPUT The analog input of the ADC1175- switch followed by and V RB RBS an integrator. The capacitance seen at the input changes ...
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... Since a dynamic capaci- tance is more difficult to drive than is a fixed capacitance, choose an amplifier that can drive this type of load. The FIGURE 3. Driving the ADC1175-50. Choose an op-amp that can drive a dynamic capacitance. 2.0 REFERENCE INPUTS The reference inputs V ...
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Applications Information FIGURE 4. Better Defining the ADC Reference Voltage. Self bias is still used, but the reference voltages are trimmed by providing a small trim current with the operational amplifiers. www.national.com (Continued) 12 DS100896-26 ...
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... Because of this, the output data tran- sition occurs very near the falling edge of the ADC clock. To avoid clocking errors, you should use the rising edge of the ADC clock to latch the output data of the ADC1175-50 and not use the falling edge. 4.0 POWER SUPPLY CONSIDERATIONS Many A/D converters draw sufficient transient current to cor- rupt their own power supplies if not adequately bypassed ...
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... I/O lines should be placed over the digital ground plane. 7.0 DYNAMIC PERFORMANCE The ADC1175- tested and its dynamic performance is guaranteed. To meet the published specifications, the clock source driving the CLK input must be free of jitter. For best ac performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree ...
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... Not considering the effect on a driven CMOS digital cir- cuit(s) when the ADC1175- the power down mode. Because the ADC1175 output goes into a high im- pedance state when in the power down mode, any CMOS device connected to these outputs will have their inputs float- ing ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 24-Lead Package JM Order Number ADC1175-50CIJM NS Package Number M24D 16 ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted (Continued) 24-Lead Package TC Order Number ADC1175-50CIMT NS Package Number MTC24 2. A critical component is any component of a life ...