MD3331-D64-V3 M-Systems Inc., MD3331-D64-V3 Datasheet - Page 22

• Manufacturer Part Number: MD3331-D64-V3
• Description: Diskonchip Millennium Plus
• Manufacturer: M-Systems Inc.

DiskOnChip Millennium Plus 16/32/64MByte
Figure 8: Standard Interface Simplified Block Diagram, 16MB Devices
3.2
System Interface
The system interface block provides an easy-to-integrate SRAM-like (also EEPROM-like) interface to DiskOnChip
Millennium Plus, enabling it to interface with various CPU interfaces, such as a local bus, ISA bus, SRAM interface,
EEPROM interface or any other compatible interface. In addition, the EEPROM-like interface enables direct access
to the Programmable Boot Block to permit XIP functionality during system initialization.
A 13-bit wide address bus enables access to the DiskOnChip 8KB memory window (as shown in Section 6.2). In
32/64MB capacities, the 16-bit data bus permits full 16-bit wide access to the flash, due to an internal, dual-bank,
interleaved architecture. With both internal and external 16-bit access, DiskOnChip Millennium Plus 32/64MB
provides unrivaled performance. In 16MB capacities, an 8-bit data bus permits 8-bit wide internal access to the flash
but 16-bit external access to the host.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and write cycles. A
write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a read cycle occurs while both the
CE# and OE# inputs are asserted. Note that DiskOnChip Millennium Plus does not require a clock signal.
DiskOnChip Millennium Plus features a unique analog static design, optimized for minimal power consumption.
The CE#, WE# and OE# signals trigger the controller (e.g., system interface block, bus control and data pipeline)
and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase. See Section 5.2 for further
details.
The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase, delay the CPU
resources. The signal is also asserted when a Data Protection violation has occurred. When this signal is
implemented, the CPU can run other tasks and only returns to continue read/write operations with DiskOnChip
Millennium Plus after the IRQ# signal has been asserted and an Interrupt Handling Routine (implemented in the OS)
has been called to return control to the TrueFFS driver.
DiskOnChip Millennium Plus contains several configuration signals. The identification signals (ID[1:0]) are used
for identifying the relevant DiskOnChip device in a cascaded configuration (see Section 9.6 on cascading for further
details). The Lock (LOCK#) signal enables hard-wire hardware-controlled protection of code and data, as described
below on protection and security-enabling features. For a standard interface, the Interface Configuration (IF_CFG)
signal configures DiskOnChip for 16-bit or 8-bit data access (see Section 9.5.4).
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Data Sheet, Rev. 1.7
93-SR-002-03-8L