MT8931C Zarlink Semiconductor, MT8931C Datasheet - Page 4

• Manufacturer Part Number: MT8931C
• Description: 4 Wire Full-duplex 2B+D (192 Kbps) Data Format Isdn S And T Subscriber Network Interface Circuit
• Manufacturer: Zarlink Semiconductor

Functional Description
The MT8931C Subscriber Network Interface Circuit
(SNIC) is a multifunction transceiver providing a
complete interface to the S/T Reference Point as
specified in ETS 300-012, CCITT Recommendation
I.430 and ANSI T1.605.
point-to-point
transmission, the SNIC may be used at either end of
the digital subscriber loop. A programmable digital
interface allows the MT8931C to be configured as a
Network
Equipment (TE) device.
The SNIC supports 192 kbit/s (2B+D + overhead) full
duplex data transmission on a 4-wire balanced
transmission line. Transmission capability for both B
and D channels, as well as related timing and
synchronization functions, are provided on chip. The
signalling capability and procedures necessary to
enable customer terminals (TEs) to be activated and
deactivated,
functionality. The SNIC handles D-channel resource
allocation and prioritization for access contention
resolution and signalling requirements in passive bus
line configurations. Control and status information
allows implementation of mainten-ance functions
and monitoring of the device and the subscriber loop.
An HDLC transceiver is included on the SNIC for link
access
Depacketized data is passed to and from the
transceiver via the microprocessor port. Two 19 byte
deep FIFOs, one for transmit and one for receive,
are provided to buffer the data. The HDLC block can
be set up to transmit or receive to/from either the
S-interface port or the ST-BUS port. Further, the
transmit destination and receive source can be
independently selected, e.g., transmit to S-interface
while receiving from ST-BUS.
receive paths can be separately enabled or disabled.
4
protocol
Termination
form
and
IRQ/NDA
R/W/WR
AS/ALE
Cmode
DS/RD
HALF
DSTo
F0od
DSTi
C4bi
VSS
handling
F0bi
CS
NT
point-to-multipoint
part
(NT)
10
11
12
13
14
1
2
3
4
5
6
7
8
9
NT MODE
of
via
or
Implementing both
The transmit and
the
as
the
Figure 3 - SNIC Pin Connections
28
27
26
25
24
23
22
21
20
19
18
17
16
15
a
MT8931C’s
D-channel.
VDD
VBias
LTx
LRx
STAR
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
voice/data
Terminal
Both, one and two byte address recognition is
supported by the SNIC. A transparent mode allows
data to be passed directly to the D channel without
being packetized.
A block diagram of the MT8931C is shown in Figure
1.
CCITT compatible S/T interface
interface), a 2048 kbit/s ST-BUS serial port, and a
general purpose parallel microprocessor port. This
8-bit parallel port is compatible with both Motorola or
Intel microprocessor bus signals and timing.
The three major blocks of the MT8931C, consisting
of the system serial interface (ST-BUS), HDLC
transceiver, and the digital subscriber loop interface
(S-interface) are interconnected by high speed data
busses.
S-interface port (B1, B2 and D channels) can be
accessed from either the parallel microprocessor
port or the serial ST-BUS port. This is also true for
SNIC control and status information (C-channel).
Depacketized D-channel information to and from the
HDLC section can only be accessed through the
parallel microprocessor port.
S-Bus Interface
The S-Bus is a four wire, full duplex, time division
multiplexed transmission facility which exchanges
information at 192 kbit/s rate including two 64 kbit/s
PCM voice or data channels, a 16 kbit/s signalling
channel and 48 kbit/s for synchronization and
overhead. The relative position of these channels
with respect to the ST-BUS is shown in Figures 4
and 5.
The SNIC makes use of the first four channels on the
ST-BUS to transmit and receive control/status and
data to and from the S-interface port. These are the
B, D and C-channels (see Figure 4).
The SNIC has three interface ports: a 4-wire
IRQ/NDA
R/W/WR
AS/ALE
DS/RD
XTAL2
XTAL1
HALF
DSTo
C4bo
F0bo
F0od
DSTi
VSS
CS
Data sent to and received from the
10
11
12
13
14
1
2
3
4
5
6
7
8
9
TE MODE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VBias
LTx
LRx
Rsto
Rsti
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
(subscriber loop
Data Sheet