MT8930C Zarlink Semiconductor, MT8930C Datasheet - Page 9

• Manufacturer Part Number: MT8930C
• Description: 4 Wire Full-duplex 2B+D (192 Kbps) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode
• Manufacturer: Zarlink Semiconductor

Data Sheet
carry data, the bit ordering must be reversed to
comply with the existing datacom standards (i.e.,
least significant bit first).
These contradicting standards place a restriction on
all information input and output through the serial
and parallel ports. Information transferred through
the serial ports, will maintain the integrity of the bit
order. Data sent to either serial port from the parallel
port, will transmit the least
Therefore,
microprocessor port must be reordered to have the
sign bit as the least significant bit.
When the microprocessor reads D, B1 or B2 channel
data of either ST-BUS or S-bus serial port, the least
significant bit read is the first bit received on that
particular channel of either serial port.
The D-channel received on the serial ST-BUS ports
must be ordered with the least significant bit first as
shown in Figure 4.
D-channel
microprocessor port.
The C-channel bit mapping from the parallel port to
the ST-BUS is organized such that the most
significant bit is transmitted or received first.
State Activation
The
deactivates the SNIC in response to line activity or
external command.
hardware driven and need not be initialized by the
microprocessor. The state diagram for initialization
is shown in Figure 7.
The protocol used by the state activation controller is
defined as follows:
1)
2)
3)
4)
5)
state
In the deactivated state, neither the NT nor
If the TE wants to initiate activation, it must
Once the NT has detected Info1, it begins to
As soon as the TE synchronizes to Info2, it
The NT will then transmit a valid frame with
TE assert a signal on the line (Info0).
begin
consisting of a positive zero, a negative zero
followed by six ones (Info1).
transmit Info2 which consists of an S-Bus
frame with zeros in the B and D-channel and
the activation bit (A-bit) set to zero.
responds with a valid S-Bus frame with data
in the B1, B2 and D-channel (Info3).
data in the B1, B2 and D-channel. It will also
directed
a
activation
transmitting
PCM
The controller is completely
to
byte
This also applies to the
controller
the
a
input
ST-BUS
significant bit first.
continuous
activates
through
from
signal
the
the
or
If the NT wishes to initiate the activation, steps 2 and
3 are ignored and the NT starts sending Info2. To
initiate a deactivation, either end begins to send
Info0 (Idle line).
D-channel Priority Mechanism
The SNIC contains a hardware priority mechanism
for D-channel contention resolution.
connected in a point-to-multipoint configuration are
allocated
approach.
accomplished by monitoring the D-echo channel
(E-bit) and incrementing the D-channel priority
counter with every consecutive one echoed back in
the E bit. Any zero found on the D-echo channel will
reset the priority counter.
There are two classes of priority within the SNIC,
one user accessible and the other being strictly
internal.
class of operation and has precedence over the
internal priority.
select the level of priority within each class (i.e., the
internal priority is a subsection of the user accessible
priority). User accessible priority selects the terminal
count as 8/9 or 10/11 consecutive ones on the E-bit
(8 being high priority while 10 being low priority).
The internal priority selects the terminal between 8
or 9 for high class and 10 or 11 for low class. The
first terminal equipment to attain the E-bit priority
count will immediately take control of the D-channel
by sending the opening flag.
terminal has the same priority, all but one of them will
eventually detect a collision. The TEs that detect a
collision will immediately stop trans-mitting on the D-
channel, generate an interrupt through the Dcoll bit,
reset the DCack bit on the next frame pulse, and
restart the counting process. The remainder of the
packet in the Tx FIFO is ignored.
After successfully completing a transmission, the
internal priority level is reduced from high to low.
The internal priority will only be increased once the
terminal count for the respective level of priority has
been achieved (e.g., if TE has high priority internally
and externally, it must count 8 consecutive ones in
the D-echo channel.
successful transmission has been completed, the
internal priority is reduced to a lower level (i.e., count
= 9). This terminal will not return to the high internal
priority
monitored on the D-echo channel).
set the activation bit (A) to binary one once
synchronization to Info3 is achieved.
until
The user accessible priority selects the
the
Allocation
9
D-channel
The latter (internal priority), will
consecutive
Once this is achieved and
of
using
the
ones
If more than one
D-channel
a
have
systematic
All TEs
been
is
9