MT8930C Zarlink Semiconductor, MT8930C Datasheet
MT8930C
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MT8930C Summary of contents
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... SNIC may be used at either end of the subscriber line (NT or TE). An HDLC D-channel protocoller is included and controlled through a Motorola/Intel microprocessor port. A controllerless mode allows the SNIC to operate without a microprocessor. The MT8930C is fabricated in Zarlink’s CMOS process. D-channel Priority Mechanism PLL HDLC Transceiver ...
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... MT8930C 28 1 HALF 2 27 C4b 26 F0b 3 25 F0od DSTi 23 DSTo 6 22 Cmode 7 CK/ R/W/WR, AFT/PRI DS/RD, DinB 10 18 AS/ALE, P/SC 11 CS, DReq 17 12 IRQ/NDA, DCack 16 13 VSS PIN PDIP Pin Description Pin # Name DIP PLCC 1 2 HALF HALF Input/Output: this is an input in NT mode and an output in TE mode identifying ...
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... Internal State Outputs (Cmode =0): Binary encoded state number outputs IS0 Description When active, marks are transmitted in the with a 10kΩ resistor. DD IS1 NT Mode 0 deactivated 1 pending deactivation 0 pending activation 1 activated MT8930C for normal operation in NT mode only Mode deactivated synchronized activation request activated 3 ...
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... MT8930C Pin Description (continued) Pin # Name DIP PLCC 17 26 SYNC/BA Synchronization/Bus Activity Output (Cmode = 0): output indicating synchronization to incoming RX frames when activation request is asserted and the deactivation request is ’0’ ( and DR = 0). Synchronization is declared once three successive frames conforming to the 14-bit bipolar violation criteria have been detected. If part is deactivated or activation request is ’ ...
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... Both, one and two byte address recognition is supported by the SNIC. A transparent mode allows data to be passed directly to the D channel without being packetized. A block diagram of the MT8930C is shown in Figure 1. The SNIC has three interface ports: a 4-wire the MT8930C’s ...
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... SNIC also has provisions for a controllerless mode (Cmode=0), where the microprocessor port is redefined to allow access to the control/status registers via external hardware. The three major blocks of the MT8930C, consisting of the system serial interface (ST-BUS), HDLC transceiver, and the digital subscriber loop interface (S-interface) are interconnected by high speed data busses ...
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Data Sheet 7 ...
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Line Code The line code used on the S-interface is a Pseudo ternary code with 100% pulse width as seen in Figure 6 below. Binary zeros are represented as marks on the line and successive marks will alternate in polarity. ...
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Data Sheet carry data, the bit ordering must be reversed to comply with the existing datacom standards (i.e., least significant bit first). These contradicting standards place a restriction on all information input and output through the serial and parallel ports. ...
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... Sync = 1 Sync = 0 Figure 7 - Link Activation Protocol, State Diagram Line Wiring Configuration The MT8930C can interface to any of the three wiring configurations which are specified by CCITT Recommendation I.430 and ANSI T1.605 (refer to Figs 10). These consist of a point-to-point or one of the two point-to-multipoint configurations (i.e., short passive bus or the extended passive bus) ...
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Data Sheet operating in adaptive timing TR is the line termination resistor = 100 Ω operating in fixed timing TR is the line termination resistor = 100 Ω Fiure 9 ...
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... MT8930C Channel Channel 0 1 Bit 7 F0b C4b ST-BUS Channel 31 BIT CELLS Bit 0 Figure 12 - Clock & Frame Alignment for ST-BUS Streams ST-BUS Interface The ST-BUS is a synchronous time division multiplexed serial bussing scheme with data streams operating at 2048 kbit/s configured as 32, 64 kbit/s channels (refer to Fig ...
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... Figure 13 - Daisy Chaining the SNIC V DD MT8930C MT8930C NT NT STAR STAR F0b F0b DSTi DSTi DSTo MT8930C MT8930C NT STAR STAR F0b F0b DSTi DSTi Figure Star Configuration Intel multiplexed bus signals and timing. MOTEL Compatible bus) uses the level of the DS/RD pin at the rising edge appropriate rising edge of AS/ALE (refer Fig ...
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... These parallel accesses must be refreshed every frame. Asynchronous registers, on the other hand, can be accessed at any time. When the Cmode pin is low, controllerless mode is selected and the parallel port reverts to hardwired control/status pins. This allows the MT8930C to function without the need for microprocessor ...
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Data Sheet Diagnostic Register cleared. Once full activation is achieved the Diagnostic Register can be written to in order to enable the various test functions. HDLC Transceiver The HDLC Transceiver handles the bit oriented protocol structure and formats the D-channel ...
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Interframe Time Fill When the HDLC Tranceiver is not sending packets, the transmitter can be in one of two states mentioned below depending on the status of the IFTF bit in the HDLC Control Register 1. i) Idle State The ...
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Data Sheet must be set HIGH, before writing the next byte into the FIFO. This bit is cleared automatically once the byte is written to the Transmit FIFO. ‘flagged’ byte reaches the bottom of the FIFO, a frame abort sequence ...
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Byte” status on any of its bytes. iv) Idle Channel While receiving the idle channel, the idle bit in the HDLC status register remains set. v) Transparent Data Transfer By setting ...
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... S-Bus. A ’0’ disables the loopback. Table 6. HDLC Control Register 1 (Read/Write Add. 00010 Note 1: The HDLC receiver must be enabled as well as the designated channel. DESCRIPTION . DESCRIPTION ( mode, the transmission of the packet is not affected. In MT8930C ) ...
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... MT8930C BIT NAME B7-B5 NA Keep at ’0’ for normal operation. B4 Trans A ’1’ will place the HDLC in a transparent mode. This will perform the serial to parallel or parallel to serial conversion without inserting or deleting the opening and closing flags, CRC bytes or zero insertion. The source or destination of the data is determined by the port selection bits in the HDLC Control Register 1 ...
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... The HDLC will always disable the receiver once the receive overflow has been detected. The receiver will be re-enabled upon detection of the next flag. Table 10. HDLC Interrupt Status Register (Read Add. 00100 Note 1: All interrupts will be reset after a read to the HDLC Interrupt Status Register. DESCRIPTION ) B DESCRIPTION ) B MT8930C 21 ...
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... MT8930C BIT NAME B7-B2 R1A7-R1A2 A six bit mask used to interrogate the first byte of the received address (where B7 is MSB). If address recognition is enabled, any packet failing the address comparison will not be stored in the Rx FIFO Not applicable to address recognition. B0 A1En If ’0’, the first byte of the address field will not be used during address recognition. ...
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... DSTi to DSTo remote loopback LRx to LTx DESCRIPTION IS0 - IS1 deactivated pending deactivation pending activation activated ’1’. (2) (Read Add. 01001 MT8930C B0 and = 1) B (1) A bus activity identifies . ) reset when 128 µ 23 ...
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... MT8930C BIT NAME B7 AR Setting this bit will initiate the activation of the S-Bus. If ’0’, the device will remain in the present state Setting this bit will initiate the deactivation of the S-Bus. If ’0’, the device will remain in the present state. This bit has priority over AR. ...
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... TE mode. Please refer to “State Machine” section of Application Note MSAN-141 for further details. DESCRIPTION IS0 - IS1 deactivated synchronized activation request activated (2) (Read Add. 01001 DESCRIPTION MT8930C (1) A bus activity identifies the . ) reset when 128 µ ...
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... Applications The MT8930C is useful in a wide variety of ISDN applications. Being used at both the Network Termination (NT) and Terminal Equipment (TE) ends of the line, the SNIC finds application on digital subscriber line cards and in full featured digital telephone sets. The SNIC can be combined with the MT8971B/72B to implement an NT1 function(with biphase line code on the U interface) as shown in Figure 16 ...
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... Data Sheet Termination Network MH89101 U Reference Point Figure 17 - NT1 using the MT8910-1 (DSLIC) and MT8930C (SNIC) MT8930C ‡ R LTx V Bias ‡ R LRx 1:2 2kΩ IRQ + Converter +5V 10k ‡ 100Ω terminating resistor Microprocessor L C4b C4b out+ F0b F0b ...
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... TE applications, this filter can also be used for NT applications allowing common hardware for TE and NT applications. K1 isolates the MT8930C from the line for multidrop applications in cases where the device is powered down 4-winding 5mH common mode choke to suppress EMI on the 4-wire line. ...
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... MT8930C applications, where stringent R1 should be chosen to 75Ω . Numerous types Rx+ Parts List: C1 0.1µF Ceramic C2 = 10µF Tantalum C4 = 22pF D1-4 = IN914 D5 IN270 Germanium ...
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... C1 MT8930C D5 LTx Bias R1 LRx Figure 21 - ETS 300-012 NT & TE Line Interface for VAC X027 or X028 MT8930C D5 LTx Bias R1 LRx Figure 22 - ETS 300-012 NT & TE Line Interface for VAC X029 or X030 ...
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... LTx Bias R2 LRx V SS Figure 23 - Proprietary NT & TE Line Interface MT8930C Tx+ Tx- Rx- Rx+ Parts List: C1 0.1µF Ceramic C2 = 10µF Tantalum D1-4 = IN914 R1 = see circuit description R3 100Ω T1 see circuit description 31 ...
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... MT8930C Absolute Maximum Ratings Parameters 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Supply Voltage 2 Input High Voltage* ...
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... SOD 320 t 0 HAS t 200 HAH ST-BUS Bit Cell t P4o t FPH C4W t C4W t t SIH SIS Figure 22 - ST-BUS Timing NT Mode MT8930C Units Test Conditions Load load load (HDLC connected to ST-BUS DFD ...
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... MT8930C AC Electrical Characteristics Characteristics 1 F0b output pulse width 2 C4b to (F0b) delay 3 C4b to (F0b) hold time 4 C4b output clock period 5 C4b pulse width High or Low 6 C4b transition time 7 F0od delay 8 F0od pulse width 9 Serial input setup time 10 Serial input hold time 11 Serial output delay ...
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... WPW t 60 RWD t 240 RPW t 20 RDS t CSS t ADH t RWD t WPW t CSS t ADH Data out t DOD t RWD t RPW MT8930C (Ref. Figure 24 & 25) Units Test Conditions load load CSH t DHW Data in t DWS t CSH t ...
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... MT8930C AC Electrical Characteristics Characteristics 1 Chip select setup time 2 Chip select hold time 3 Address strobe pulse width 4 Data strobe setup time 5 Data strobe hold 6 Data strobe pulse width 7 Read/Write setup time 8 Read/Write hold time 9 Address setup time 10 Address hold time 11 Data setup time - Write ...
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... IRQ, Rsti Timing (Ref. Figure 28) ‡ Sym Min Typ Max t 100 IRD t 1 RSW t IRD t RSW Figure 28 - INT & Rsti Timing MT8930C Units Test Conditions load load IS0 & IS1 MFR (TE Mode) MCH (NT Mode) M/S (TE Mode) Units Test Conditions ns µ ...
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... MT8930C Notes: 38 Data Sheet ...
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