MT9315 Zarlink Semiconductor, MT9315 Datasheet - Page 8

• Manufacturer Part Number: MT9315
• Description: Acoustic Echo CANceller
• Manufacturer: Zarlink Semiconductor

Advance Information
Linear PCM
The 16-bit 2’s complement PCM linear coding
permits a dynamic range beyond that which is
specified in ITU-T G.711 for companded PCM. The
echo-cancellation algorithm will accept 16 bits 2’s
complement linear code which gives a maximum
signal level of +15dBm0.
Bit Clock (BCLK/C4i)
The BCLK/C4i pin is used to clock the PCM data in
both SSI (BCLK) and ST-BUS (C4i) operations.
In SSI operation, the bit rate is determined by the
BCLK frequency. This input must contain either eight
or sixteen clock cycles within the valid enable strobe
window. BCLK may be any rate between 128 KHz to
4.096 MHz and can be discontinuous outside of the
enable strobe windows defined by ENA1, ENA2 pins.
Incoming PCM data (Rin, Sin) are sampled on the
falling edge of BCLK while outgoing PCM data (Sout,
Rout) are clocked out on the rising edge of BCLK.
See Figure 11.
In ST-BUS operation, connect the system C4
(4.096MHz) clock to the C4i pin.
Master Clock (MCLK)
A nominal 20MHz master clock (MCLK) is required.
The MCLK input may be asynchronous with the
8KHz frame.
Microport
The serial microport provides access to all MT9315
internal read and write registers. This microport is
compatible with Intel MCS-51 (mode 0), Motorola
SPI
Semiconductor
PCM Code
+ Full Scale
- Full Scale
+ Zero
- Zero
(CPOL=0,
Table 4 - Companded PCM
Sign-Magnitude
LAW = 0 or 1
FORMAT=0
1111 1111
1000 0000
0000 0000
0111 1111
Microwire
/A-LAW
CPHA=0),
1000 0000
1111 1111
0111 1111
0000 0000
LAW = 0
specifications.
-LAW
ITU-T (G.711)
FORMAT=1
and
1010 1010
1101 0101
0101 0101
0010 1010
LAW =1
A-LAW
National
The
microport consists of a transmit/receive data pin
(DATA1), a receive data pin (DATA2), a chip select
pin (CS) and a synchronous data clock pin (SCLK).
The MT9315 automatically adjusts its internal timing
and pin configuration to conform to Intel or Motorola/
National requirements. The microport dynamically
senses the state of the SCLK pin each time CS pin
becomes active (i.e. high to low transition). If SCLK
pin is high during CS activation, then Intel mode 0
timing is assumed. In this case DATA1 pin is defined
as a bi-directional (transmit/receive) serial port and
DATA2 is internally disconnected. If SCLK is low
during CS activation, then Motorola/National timing
is assumed and DATA1 is defined as the data
transmit pin while DATA2 becomes the data receive
pin. The MT9315 supports Motorola half-duplex
processor mode (CPOL=0 and CPHA=0). This
means that during a write to the MT9315, by the
Motorola processor, output data from the DATA1 pin
must be ignored. This also means that input data on
the DATA2 pin is ignored by the MT9315 during a
valid read by the Motorola processor.
All data transfers through the microport are two bytes
long. This requires the transmission of a Command/
Address byte followed by the data byte to be written
to or read from the addressed register. CS must
remain low for the duration of this two-byte transfer.
As shown in Figures 8 and 9, the falling edge of CS
indicates to the MT9315 that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
between the MT9315 and the microcontroller. At the
end of the two-byte transfer, CS is brought high again
to terminate the session. The rising edge of CS will
tri-state the DATA1 pin. The DATA1 pin will remain tri-
stated as long as CS is high.
Intel processors utilize Least Significant Bit (LSB)
first transmission while Motorola/National processors
use Most Significant Bit (MSB) first transmission.
The MT9315 microport automatically accommodates
these two schemes for normal data bytes. However,
to ensure timely decoding of the R/W and address
information, the Command/Address byte is defined
differently for Intel and Motorola/National operations.
Refer to the relative timing diagrams of Figure 8 and
Figure 9.
Receive data bits are sampled on the rising edge of
SCLK while transmit data is clocked out on the falling
edge of SCLK. Detailed microport timing is shown in
Figure 13 and Figure 14.
MT9315
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